FEDL22660-01
ML22660
■
Timing chart
●
Power-on timing
Be sure to input "L" to the RESETB pin before inputting the first command after power-on.
Be sure to enter "L" at the RESETB pin when the DV
DD
is below the (recommended) operating voltage range.
●
Power-off timing
Shut down each power supply after changing to the power down status with PDWN commands.
DV
DD
Status
Power-down
Shut down in order of IOV
DD
, SPV
DD
, and DV
DD
or SPV
DD
, IOV
DD
, and DV
DD
.
It is possible that the IOV
DD
shuts down and then the SPV
DD
and DV
DD
shut down at the same time,
or the SPV
DD
shuts down and then the IOV
DD
and DV
DD
shut down at the same time.
The DV
DD
, SPV
DD
and IOV
DD
can also shut down at the same time.
SPV
DD
IOV
DD
90%
DV
DD
VIH
VIL
t
RST
RESETB
After the power is turned on, the device enters the power-down state.
Start up in order of DV
DD
, SPV
DD
and IOV
DD
or DV
DD
, IOV
DD
and SPV
DD
.
It is possible that the DV
DD
and SPV
DD
start up at the same time and then the IOV
DD
starts up, or the DV
DD
and IOV
DD
start up at the same time and then the SPV
DD
starts up.
The DV
DD
, SPV
DD
and IOV
DD
can also start up at the same time.
t
RST
is specified based on the last power-on pin.
SPV
DD
IOV
DD
90%
Status
Power-down
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Summary of Contents for LAPIS Semiconductor ML22660
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