FEDL22660-01
ML22660
RST counter overflow detection
The overflow detection of RST counter is set by RSTEN bits of SAFE command. RST counter operates when any error is
detected. When the detection operation is started, the detection does not stop even if the RSTEN bit is set to "0". When the
RST counter overflows, the error bit (RSTERR) is set to "1".
Error bit (RSTERR) can be read with RDERR command. Also, error bit (RSTERR) can be cleared by ERRCL command.
The count time of the RST-counter is 2s, the initial-value. The counting time can be set to 125ms, 500ms, 2s or 4s. In addition,
the RST counter overflow can cause a transition to the command standby state after power-up.
Set the counting time and overflow operation with the dedicated tools (Speech LSI Utility).
The operation when RSTEN is set to "1" is as follows.
*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.
RSTEN
Set RSTEN = "1"
RST counter
Overflow
RSTERR
Command
SAFE
Count-up
0h
STATUSn pin
*1
n:1 or 2
Clears the RST-counter with ERRCL commands.
The RST counter stops operating.
Signal to shift command
standby state after power-up
ERRCL
0h
Error detection
RDERR
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Summary of Contents for LAPIS Semiconductor ML22660
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