Renesas M16C FAMILY, User Manual

Page: 18 / 369

Rev.2.00 Oct 16, 2006 page 7 of 354
REJ09B0340-0200
M30245 Group 2. Timer A
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer re 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF
16
- the set value + 1] becomes the frequency division
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be-
comes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate.
(5) Writing to the timer
To write to the timer register when a count is in progress, the value is written only to the reload register.
When writing to the timer register when a count is stopped, the value is written both to the reload
register and to the counter. Write a value in 16-bit units.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, pulses are output regardless of the contents of the port direction
register. To input an external signal to the timer, set the port direction register to input.
(7) Pins related to timer A
(a) TA0
IN
, TA1
IN
, TA2
IN
, TA3
IN
, TA4
IN
Input pins to timer A.
(b) TA0
OUT
, TA1
OUT
, TA2
OUT
, TA3
OUT
, TA4
OUT
Output pins from timer A. They become input pins to
timer A when event counter mode is active.
(8) Registers related to timer A
Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show
timer A-related registers.