Renesas M16C FAMILY, User Manual

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Rev.2.00 Oct 16, 2006 page 241 of 354
REJ09B0340-0200
M30245 Group 2. DMAC
(6) Reading to a register
The reload register can be read to, as in normal conditions.
(7) Switching function
(a) Switching between one-shot transfer and repeated transfer
'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows.
'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter under-
flows. The reload is carried out for the transfer counter and on the address pointer subjected to
forward direction.
The following examples are described in section 2.10.2 and 2.10.3.
• A fixed address from an arbitrary 1M byte space, one-shot transfer
• An arbitrary 1M byte space from a fixed address, repeated transfer
(8) Registers related to DMAC
Figure 2.10.1 shows the memory map of DMAC-related registers, and Figures 2.10.2 and 2.10.4 show
DMAC-related registers.
Figure 2.10.1. Memory map of DMAC-related registers
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA0 destination pointer (DAR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002C
15
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003C
16
004C
16
004E
16
0050
16
0052
16
DMA2 interrupt control register (DM2IC)
DMA3 interrupt control register (DM3IC)
0180
16
0181
16
0182
16
0183
16
0184
16
0185
16
0186
16
0187
16
0198
16
0189
16
018C
15
0190
16
0191
16
0192
16
0193
16
0194
16
0195
16
0196
16
0197
16
0198
16
0199
16
019C
16
03B0
16
03B1
16
03B2
16
03B8
16
03B9
16
03BA
16
DMA2 control register (DM2CON)
DMA2 transfer counter (TCR2)
DMA2 destination pointer (DAR2)
DMA3 control register (DM3CON)
DMA3 source pointer (SAR3)
DMA3 transfer counter (TCR3)
DMA3 destination pointer (DAR3)
DMA2 source pointer (SAR2)
DMA2 cause select register (DM2SL)
DMA3 cause select register (DM3SL)