Renesas M16C FAMILY, User Manual

Page: 245 / 369

Rev.2.00 Oct 16, 2006 page 234 of 354
REJ09B0340-0200
M30245 Group 2. A/D Converter
Table 2.9.11. Variation of the successive comparison register and Vref while A/D conversion is in
progress (8-bit mode)
Figure 2.9.20. Theoretical A/D conversion characteristics (8-bit mode)
1
1
n
9
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
n
9
n
8
1 0 0 0 0 0 0 0
n
9
n
8
n
7
n
6
n
5
n
4
n
3
1 0 0
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
0 0
b9 b0
1st comparison result
2nd comparison result
Successive approximation register
V
ref
change
A/D converter stopped
1st comparison
2nd comparison
3rd comparison
8th comparison
Conversion
complete
± ±
2
V
REF
4
V
REF
8
V
REF
± ...... ±
V
REF
256
–
2048
V
REF
[V]
2
V
REF
[V]
–
2
V
REF
2048
V
REF
[V]
±
2
V
REF
4
V
REF
–
2048
V
REF
[V]
± ±
2
V
REF
4
V
REF
8
V
REF
–
2048
V
REF
[V]
4
4
V
REF
n
9
= 1 +
V
REF
n
9
= 0 –
8
V
REF
n
8
= 1 +
8
V
REF
n
8
= 0 –
This data transfers to bit 0 to
bit 7 of AD register i.
00
16
01
16
02
16
03
16
FE
16
FF
16
Result of A/D conversion
Analog input voltage
x 2
V
REF
256
V
REF
256
x 3
x 4
V
REF
256
V
REF
256
x 254
V
REF
256
x 255
V
REF
V
REF
2048
x 3
Theoretical A/D conversion
characteristic of general 8-bit
A/D converter
0
V
REF
256
x 1
Theoretical A/D conversion
characteristic in the 8-bit mode