Rev.2.00 Oct 16, 2006 page 56 of 354
REJ09B0340-0200
M30245 Group
2. UART
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the transfer rate register can be selected from f
1
, f
8
, f
32
, and the input
from the CLK pin. Clocks f
1
, f
8
, f
32
are derived by dividing the CPU’s main clock by 1, 8, and 32
respectively.
Baud rate
(bps)
BRG's
count source
System clock : 16MHz
System clock : 7.3728MHz
BRG's set value : n
Actual time (bps)
BRG's set value : n
600
1200
2400
4800
9600
14400
19200
28800
31250
f
8
f
8
f
1
f
1
f
1
f
1
f
1
f
1
207 (CF
16
)
103 (67
16
)
51 (33
16
)
207 (CF
16
)
103 (67
16
)
68 (44
16
)
51 (33
16
)
34 (22
16
)
33 (21
16
)
601
1202
2404
4808
9615
14493
19231
28571
31250
95 (5F
16
)
47 (2F
16
)
23 (17
16
)
95 (5F
16
)
47 (2F
16
)
31 (1F
16
)
23 (17
16
)
15 (F
16
)
600
1200
2400
4800
9600
14400
19200
28800
Actual time (bps)
f
8
Table 2.4.2. Example of baud rate setting
Table 2.4.3. Error detection
Type of error
When the flag turns on
Description
How to clear the flag
• This error occurs when the
serial interface starts receiving
the next data item before
reading the contents of the
UARTi receive buffer register
and receives the bit preceding
the final stop bit of the next
data item.
• The contents of the UARTi
receive buffer register are
undefined.
• The UARTi receive interrupt
request bit does not go to “1”.
• This error occurs when the
stop bit falls short of the set
number of stop bits.
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
T
h
e
e
r
r
o
r
i
s
d
e
t
e
c
t
e
d
w
h
e
n
d
a
t
a
i
s
t
r
a
n
s
f
e
r
r
e
d
f
r
o
m
t
h
e
U
A
R
T
i
r
e
c
e
i
v
e
r
e
g
i
s
t
e
r
t
o
t
h
e
U
A
R
T
i
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
.
•
S
e
t
t
h
e
s
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
b
i
t
s
t
o
“
0
0
0
2
”
.
•
S
e
t
t
h
e
r
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
t
o
“
0
”
.
•
W
h
e
n
a
l
l
e
r
r
o
r
(
o
v
e
r
r
u
n
,
f
r
a
m
i
n
g
,
a
n
d
p
a
r
i
t
y
)
a
r
e
r
e
m
o
v
e
d
,
t
h
e
f
l
a
g
i
s
c
l
e
a
r
e
d
.
• Set the serial I/O mode select
bits to ”000
2
”.
• Set the receive enable bit to
“0”.
• Read the lower-order byte of
the UARTi receive buffer
register.
Overrun error
F
r
a
m
i
n
g
e
r
r
o
r
P
a
r
i
t
y
e
r
r
o
r
E
r
r
o
r
-
s
u
m
f
l
a
g
(3) An error detection
In UART mode, detected errors are shown in Table 2.4.3.
Summary of Contents for M16C FAMILY
Page 12: ...Chapter 1 Hardware...
Page 13: ...See M30245 group datasheet...
Page 14: ...Chapter 2 Peripheral Functions Usage...
Page 303: ...THIS PAGE IS BLANK FOR REASONS OF LAYOUT...
Page 304: ...Chapter 3 Examples of Peripheral Functions Applications...
Page 340: ...Chapter 4 External Buses...
Page 361: ...THIS PAGE IS BLANK FOR REASONS OF LAYOUT...
Page 362: ...Chapter 5 Standard Characteristics...
