Renesas M16C FAMILY, User Manual

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Rev.2.00 Oct 16, 2006 page 207 of 354
REJ09B0340-0200
M30245 Group 2. USB function
2.8.8 USB Operation (Interface with DMAC Transfer)
The M30245 group can select a USB (USB0/USB1/USB2/USB3) as the DMA request factor. The USB0
corresponds to DMA0, USB1 to DMA1, USB2 to DMA2, and USB3 to DMA3. The DMA request factor
origin of USB0/USB1/USB2/USB3 is also set by setting any one of endpoints 1 to 4 IN/OUT factors to
USB DMAx(x=0 to 3) request register .
The DMA request factor of USB0/USB1/USB2/USB3 occurs, under particular conditions, not only on
occurrence of an interrupt request of each endpoint but also on write/read to/from IN/OUT FIFO.
(1) Related Registers
●
USB DMAx(x=0 to 3) request register
This register sets the DMA request factor origin of USB0/USB1/USB2/USB3. When, under particular
conditions, write/read to/from the FIFO of the endpoint selected by this register or an event such as
the endpoint's interrupt request occurs, a DMA request occurs. This register can be set “1” only to 1
bit. When multiple bits are simultaneously set to “1”, the setting becomes invalid. Other DMA related
registers also need to be set before a valid value is set; for example, “00011
2
” (USB0/USB1/USB2/
USB3) is set to DMA request cause select bits (b4,b3,b2,b1,b0) of DMAx(x=0 to 3) request cause
select register (addresses 03B8
16
, 03BA
16
, 03B0
16
, 03B2
16
).
The configuration of USB DMAx(x=0 to 3) request register is shown in Figure 2.8.50.
Bit Symbol
Bit Name
Function
R W
Symbol
USBDMAx
(x=0 to 3)
Address
When reset
USB DMAx Request registers
b7
(b15)
(b8)
b0
DMAxR1
DMAxR2
DMAxR3
DMAxR4
DMAxR6
DMAxR7
DMAxR8
DMAxR9
b7 b0
EP1 IN FIFO write request select bit
EP2 IN FIFO write request select bit
EP3 IN FIFO write request select bit
EP4 IN FIFO write request select bit
EP1 OUT FIFO read request select bit
EP2 OUT FIFO read request select bit
EP3 OUT FIFO read request select bit
EP4 OUT FIFO read request select bit
O O
Reserved O O
0 : Not selected
1 : Selected
0 0 0 0 0
0290
16
, 0292
16
,
0294
16
, 0296
16
0000
16
Must always be set to “0”
0
0 0
Reserved O O
Must always be set to “0”
0 : Not selected
1 : Selected
Reserved
O O Must always be set to “0”
O O
Figure 2.8.50. USB DMAx(x=0 to 3) request register