Renesas M16C FAMILY, User Manual

Page: 81 / 369

Rev.2.00 Oct 16, 2006 page 70 of 354
REJ09B0340-0200
M30245 Group 2. UART
Figure 2.4.11. Set-up procedure of reception in UART mode (1)
Continued to the next page
Setting UART transmit/receive control register 1 (i=0 to 3)
Setting UARTi transmit/receive mode register (i=0 to 3)
UARTi transmit/receive mode register
UiMR [Address 03A8
16
, 368
16
, 0338
16
, 328
16
]
Setting UARTi transmit/receive control register 0 (i=0 to 3)
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
BRG count source select bit
b1 b0
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Inhibited
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Data output select bit (Note)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CTS/RTS disable bit
0 : CTS/RTS function enabled
UARTi transmit/receive control register 0
UiC0 [Address 03AC
16
, 36C
16
, 033C
16
, 32C
16
]
Transfer format select bit
0 : LSB first
0 0 0 0 1
Note: UART2 transfer pin (TxD2: P7
0
and SCL2: P7
1
) is N-channel open drain output.
It cannot be set to CMOS output.
Note: Set the RxDi pin's port direction register to “0” when receiving.
Must be fixed to “0” in UART mode
b7 b0
Data logic select bit
0 : No reverse
Error signal output enable bit (in UART mode)
0 : Output disabled
0 0 0
b7 b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD
16
, 36D
16
, 033D
16
, 32D
16
]
0 0 1 0 1
Internal/external clock select bit
0 : Internal clock
Serial I/O mode select bit (Note)
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Stop bit length select bit
0 : One stop bit
T
X
D, R
X
D I/O polarity reverse bit
Usually set to “0”
Valid when bit 6 = “1”
b7 b0
Must be fixed to “0” in UART mode
0 0
Parity enable bit
0 : Parity disabled