PPC7A Product Manual
Functional Description
8-16
1
st
Edition
Semaphore Register
The Universe II provides a 32-bit register containing four semaphores, one in each byte.
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Each of the four semaphores is a 7-bit data field plus a 1-bit lock field
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Ownership of the semaphore is obtained by writing a unique value to the 7-bit field while
setting the lock bit
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The write is only accepted if the lock bit is not already set
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Ownership can be confirmed by reading back the value in the 7-bit field after the write, and
comparing it with the unique value written
The semaphores provide a locking mechanism that can be used to guarantee exclusivity of access to
system resources shared between:
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Multiple processes
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Processes and bus masters (PCI or VME)
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Bus masters (PCI or VME)
VMEbus Location Monitor
The Universe II contains a VMEbus location monitor for interrupts and message passing.
VMEbus Interrupts
If programmed to do so, the Universe II responds to a VMEbus interrupt with a VMEbus interrupt
acknowledge cycle. The Universe captures the status/ID and then raises an interrupt on the PCI bus. No
further VMEbus interrupts are handled on that level until the processor reads the status/ID and re-arms
the interrupt handler.
The Universe II can be programmed to generate any level of VMEbus interrupt. It can raise an interrupt
on the PCI bus when the VMEbus interrupt has been acknowledged.
Seven software interrupts in the Universe II allow an interrupt to be generated on any of the seven
VMEbus IRQs.
VME Bus Errors
Assertion of BERR~ during a coupled VMEbus master cycle causes a target-abort (bus error) on the PCI
bus. A PCI bus target-abort during a coupled VMEbus slave cycle causes BERR~ on the VMEbus. See
the Machine Check Exception section for further details of target abort.
A bus error during posted write transfers raises an interrupt (if enabled) to the processor. Several options
are available, including stopping the operation and purging the offending transaction.
A bus error during a DMA operation raises an interrupt and stops the DMA operation on the bus where
the error was detected.
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