PPC7A Product Manual
Functional Description
8-2
1
st
Edition
PowerPC Processor
MPC7455
The PPC7A is based around the MPC7455 PowerPC chip. This device contains:
•
A 32-bit implementation of the PowerX architecture
•
32 Kbytes, 8-way set associative instruction and data caches
•
On chip 256 Kbytes of L2 cache
•
A separate 64-bit wide, two-way set associative L3 cache bus
The processor has a 32-bit physical address bus and a 64-bit data bus.
P
ROCESSOR
T
YPE
B
US
F
REQUENCY
(M
HZ
) L3 F
REQUENCY
(M
HZ
) C
ORE
F
REQUENCY
(M
HZ
)
MPC7455
100
166 to 266
500 and above
L3 Cache
The L3 cache has the following features:
•
Two-way set associative
•
32-byte line size
•
64 bits wide
•
Capable of operating in write-through or write-back modes
•
Operation at speeds up to 266 MHz through a dedicated L3 cache bus interface
•
Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 (i.e. SDRAM)
•
Entries in write-through mode can be valid or invalid
•
Entries in write-back mode can be invalid, valid-unmodified or valid-modified
Having the L3 cache controller inside the MPC7455 allows performance to be further enhanced by
parallel compares on L1, L2 and L3 tags, and filtering L3 cache traffic from the system bus. Full
coherency on the system bus can be maintained.
L3 cache access times from the processor for a 32-byte burst are:
200 M
HZ
L3 I
NTERFACE
T
RANSFER
R
ATE
Burst read hit non-pipelined
3,1,1,1
1066 Mbytes/second
Burst read hit pipelined
1,1,1,1
1600 Mbytes/second
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