PPC7A Product Manual
Connectors
5-15
1
st
Edition
PMC Signal Descriptions
M
NEMONIC
S
IGNAL
D
ESCRIPTION
AD0 to AD63
Address/Data bits. Multiplexed address and data bus
C_BE0 to C_BE7
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry
out on the PCI bus. During the data phase the signals are byte enables that specify the active bytes
on the bus
FRAME~
FRAME. Driven low by the current master to signal the start and duration of an access
DEVSEL~
Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of the
current access
PAR
Parity. Parity protection bit for AD0 to AD31 and BE0 to BE3
PARR64
Parity. Parity protection bit for AD32 to AD63
IRDY~
Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
LOCK~
LOCK. Driven low to indicate an atomic operation that may require multiple transactions to complete
BUSMODE1~
Bus Mode 1. Driven low by a PMC if it supports the current bus mode
BUSMODE2~,
BUSMODE3~ and
BUSMODE4~
Bus mode. Driven by the host to indicate the bus mode. On the PPC7A
this is always PCI.
BUSMODE2~ is only connected to a 4.7 k
Ω
pull-up. BUSMODE3~ and BUSMODE4~ are connected
to GND.
RST~
Reset. Driven low to reset the PCI bus
TRDY~
Target Ready. Driven low by the current target to signal its ability to complete the current data phase
PERR~
Parity Error. Driven low by a PCI agent to signal a parity error
SERR~
System Error. Driven low by a PCI agent to signal a system error
STOP~
STOP. Driven low by a PCI target to signal a disconnect or target-abort
INTA~ to INTD~
Interrupt lines. Level-sensitive, active-low interrupt requests
CLK
Clock. All PCI bus signals except RST~ are synchronous to this clock.
REQA/B~
Request. Driven low by a PCI agent to request ownership of the PCI bus
GNTA/B~
Grant. Driven low by the arbiter to grant PCI bus ownership to a PCI agent
IDSELA/B
Initialisation Device Select. Device chip select during configuration cycles
NC
No connection
REQ64~
Request 64 Bit. Driven low by PCI master to request 64 bit transfer
ACK64~
Acknowledge 64 Bit. Driven low by PCI agent in response to REQ64
TCK
Test Clock. Clock for the PMC JTAG
TMS
Test Mode Select. Select Test Mode for PMC JTAG
TRST~
Test Reset. Reset any PMC JTAG devices
TDI
Test Data In. Input data for PMC JTAG chain
TDO
Test Data Out. Data from a PMC JTAG chain
$
Note:
The PPC7A supports PMC clocking at speeds up to 66 MHz. However, if a PMC is fitted to the PPC7A that
does not support the 66 MHz clocking speed, then
both
sites are limited to 33 MHz.
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