PPC7A Product Manual
Functional Description
8-3
1
st
Edition
MPC7410
The PPC7A is based around the MPC7410 PowerPC chip. This device contains
•
A 32-bit implementation of the PowerX architecture
•
32 Kbytes, 8-way set associative instruction and data caches
•
A separate 64-bit wide, two-way set associative L2 cache bus
The processor has a 32-bit physical address bus and a 64-bit data bus.
P
ROCESSOR
T
YPE
B
US
F
REQUENCY
(M
HZ
) L2 F
REQUENCY
(M
HZ
) C
ORE
F
REQUENCY
(M
HZ
)
MPC7410
100
166 to 266
500 and above
L2 Cache
The L2 cache has the following features:
•
Two-way set associative
•
32-byte line size
•
64 bits wide
•
Capable of operating in write-through or write-back modes
•
Operation at speeds up to 266 MHz through a dedicated L2 cache bus interface
•
Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 (i.e. SDRAM)
•
Entries in write-through mode can be valid or invalid
•
Entries in write-back mode can be invalid, valid-unmodified or valid-modified
Having the L2 cache controller inside the MPC7410 allows performance to be further enhanced by
parallel compares on L1 and L2 tags, and filtering L2 cache traffic from the system bus. Full coherency
on the system bus can be maintained.
L2 cache access times from the processor for a 32-byte burst are:
200 MHZ L3 INTERFACE
TRANSFER RATE
Burst read hit non-pipelined
3,1,1,1
1066 Mbytes/second
Burst read hit pipelined
1,1,1,1
1600 Mbytes/second
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