PPC7A Product Manual
Functional Description
8-6
1
st
Edition
Memory
Controller
The Galileo GT64260 device provides an SDRAM memory controller and a FLASH interface.
Maps
The PPC7A
supports programmable memory maps. No memory maps are provided in this manual as no
memory locations are fixed in hardware. Please refer to the manuals for the software that is installed on
the PPC7A
for more information.
SDRAM
The following table shows the options available for SDRAM on-board the PPC7A:
S
DRAM
S
IZE
(M
BYTES
)
B
ANKS
S
DRAM
O
RGANISATION
64
1
8M x 8
128
2
8M x 8
128
1
16M x 8
256
2
16M x 8
256
1
32M x 8
512
2
32M x 8
The SDRAM is protected by eight ECC bits per 64 data bits. All single bit, double bit and nibble errors
can be detected, and single bit errors can be corrected.
Following a hard reset, the Galileo GT64260 PCI Bridge/Memory Controller must be set up for the size
and number of banks of SDRAM and the appropriate number of wait states to match the SDRAM speed.
This is done by the standard Boot firmware. The size of the SDRAM may be checked by reading the
Memory Configuration register (see the Control and Status Registers section).
At least 100
µ
s must have elapsed from the negation of reset before enabling the SDRAM. After being
enabled, the SDRAM must not be accessed until at least 8 refreshes have occurred. If ECC is to be
enabled, then it is necessary to initialize the SDRAM to set-up valid ECC bits.
SDRAM access times from the processor, for a 32 byte burst are shown in the table:
B
US
S
PEED
C
LOCKS
A
CCESS
D
ATA
T
RANSFER
R
ATE
100 Mhz
(no page hit)
16:1:1:1
168 Mbytes/sec
100 Mhz
(pipelined)
5:1:1:1
400 Mbytes/sec
100 Mhz
(pipelined & page hit)
2:1:1:1
640 Mbytes/sec
SDRAM access times from the PCI, referenced to the 33 MHz PCI clock, for a 32-byte burst with no
interference from L1, L2 or L3 caches, are shown in the table:
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