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PPC7A Product Manual

Functional Description

8-14

1

st

Edition

Keyboard and Mouse Controller

A PS/2 compatible Keyboard and Mouse interface with Phoenix BIOS is integrated into the Ultra I/O.
Connections to the mouse and keyboard are through the P2 connector. This interface is not available if
the USB build option is fitted. See Chapter 5 for pinouts.

VMEbus Interface

The Tundra Semiconductors CA91C142 Universe II PCI to VME bridge provides the VMEbus
interface. This complies with the VME64 specification and provides:

•

All slot 1 (system controller) functions

•

Interrupt control

•

A DMA controller

•

Interprocessor communications

•

Block transfer support

Appendix A details the VMEbus compliance and basic VMEbus performance of the PPC7A.

$

Note:

The Universe II does not self-address.

VMEbus Master Access

Four general-purpose, software-programmable PCI slave images are available for access to the VMEbus.

•

All of these can be configured to access VMEbus A32, A24 or A16 address space

•

An offset may be applied to translate the local address to a different address on the VMEbus,
allowing any local address to access any VMEbus address

•

The start and end addresses of the A32, A24 and A16 PCI slave images may be set on any
64 Kbyte boundary in PCI memory or I/O space that is not allocated to other PCI-attached
devices or the user FLASH

•

One image may be set on 4 Kbyte boundaries to accommodate access to A16 space

One further, special purpose, PCI slave image allows mapping of A16 and A24 space.

•

This slave image uses a 64 Mbyte window, aligned to any 64 Mbyte address in PCI memory
space

•

The window is divided into four 16 Mbyte quadrants

•

The top 64 Kbytes of each quadrant maps to A16 space, while the rest of each quadrant maps to
A24 space

•

The Address Modifiers generated are software configurable for each quadrant

VMEbus master cycles may be coupled or write posted.

•

Coupled cycles are retried on the PCI bus until the Universe II has ownership of the VMEbus
and are not terminated on the PCI bus until all data has been transferred over the VMEbus

•

Posted writes are queued in a FIFO until the VMEbus is available for the data to be transferred

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Summary of Contents for PMCGA1-101

Page 1: ...derutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective own...

Page 2: ...PPC7A Product Manual Publication No PPC7A 0HH 1st Edition April 2003 Radstone Technology PLC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...ervices concerned The Company reserves the right to alter without notice the specification design price or conditions of supply of any product or service Trademarks The Radstone name Radstone and PowerXtreme logos and are trademarks of Radstone Technology PLC All other company and product names are acknowledged as being the trademarks or registered trademarks of their respective companies Document...

Page 4: ...eneral Description 2 1 Introduction 2 1 Features 2 2 Functional Overview 2 3 PowerPC Platform 2 3 Processor 2 4 PCI 2 5 Memory 2 6 VMEbus Interface 2 7 Utility I O and Auxiliary Function Bus 2 7 Input Output 2 7 Software Support 2 8 Boot Firmware 2 8 Built In Test 2 8 Background Condition Screening 2 8 Operating System Support 2 8 Build Styles 2 9 Level 1 2 9 Level 2 2 10 Level 3 2 10 Level 4 2 10...

Page 5: ...5 11 PMC Connector Pinouts 5 12 J11 and J21 5 12 J12 and J22 5 13 J13 and J23 5 14 PMC Signal Descriptions 5 15 J14 PMC I O 5 16 J24 PMC I O and Partial P2 Option 5 17 P10 PLD Connector Pinout 5 18 P8 RISCWatch Connector Pinout 5 18 P8 Signal Descriptions 5 19 EST Emulator Connection 5 19 Chapter 6 Front Panel 6 1 Air cooled Versions 6 1 PMC Slots 6 1 LEDs 6 1 Switches 6 1 Conduction cooled Versio...

Page 6: ...ter Block Transfers 8 15 VMEbus Slave Block Transfers 8 15 Mailboxes 8 15 Semaphore Register 8 16 VMEbus Location Monitor 8 16 VMEbus Interrupts 8 16 VME Bus Errors 8 16 VMEbus Retries 8 17 VMEbus Reset Options 8 17 Watchdog Timers 8 17 Software Programmable LEDs 8 18 Control and Status Registers 8 19 Memory Configuration Register Port 0x0804 8 20 Memory Configuration Extend Register Port 0x0806 8...

Page 7: ...nterrupts and Error Reporting 8 35 System Resets 8 35 Machine Check Exception 8 35 System Management Interrupt SMI 8 35 External Interrupt INT 8 36 PCI Interrupts 8 36 PCI Configuration 8 37 Keylock 8 37 Chapter 9 Technical Assistance 9 1 Radstone Contact Information 9 1 Troubleshooting 9 2 Appendix A Specifications A 1 VMEbus Compliance A 2 Local Resources A 3 EMC Regulatory Compliance and Safety...

Page 8: ...n whatever the market Communications Local connection of Ultra SCSI Video graphics and VME64 uses PCI as do the two IEEE P1386 1 PMC sites PMCs available directly from Radstone include high performance graphics MIL STD 1553 serial ATM FLASH memory Solid State Hard Disk fast Ethernet and other communications The PPC7A is the latest of Radstone s VME products to use 5 row connectors for P1 VME P2 I ...

Page 9: ...of configuration installation and power up as simple and user friendly as possible a certain amount of background knowledge on these subjects is assumed In the Functional Description chapter a higher degree of background knowledge is assumed on subjects including Single board computer architecture Peripherals The VMEbus Communications There is a glossary provided at the back of this manual that ex...

Page 10: ...manual s objectives audience scope structure and conventions safety notices and associated documentation Chapter 2 is a slightly more detailed but still general product description Chapter 3 contains inspection instructions and describes product identification Chapter 4 describes board configuration Chapter 5 describes the PPC7A s connectors and signals used Chapter 6 describes the PPC7A s front p...

Page 11: ... electrical equipment in such an environment constitutes a definite safety hazard Keep Away From Live Circuits If lethal voltages are present in the equipment do not remove equipment covers In these circumstances only Factory Authorised Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment...

Page 12: ...he following European Norms EN55022 CISPR 22 Radio Frequency Interference EN50082 1 IEC80 2 IEC801 3 IEC801 4 Electromagnetic Immunity The product also fulfils EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC The board product was tested in a representative system to show compliance with the above mentioned requirements A proper installation in a ...

Page 13: ...anings of 103 106 and 109 respectively The only exception to this is in the description of the size of memory areas when K M and G mean 210 220 and 230 respectively Note When describing transfer rates k M and G mean 10 3 10 6 and 10 9 not 2 10 2 20 and 2 30 In PowerX terminology multiple bit fields are numbered from 0 to n where 0 is the MSB and n is the LSB PCI and VMEbus terminology follows the ...

Page 14: ...pment and Data Communications Equipment Employing Serial Binary Data Interchange December 1991 Electronic Industries Association DC20006 USA ANSI EIA TIA 422 B Electrical Characteristics of Balanced Voltage Digital Interface Circuits December 1978 Electronic Industries Association DC20006 USA PowerPC Microprocessor Family The Programming Environments 1994 IBM VT 05452 4299 or Motorola AZ 85036 USA...

Page 15: ... Some useful sites are Motorola PowerX data is available through this site http e www motorola com IBM PowerX data is available through this site http www chips ibm com Universe II chip information including the user manuals as Adobe Acrobat PDF files is available through this site http www tundra com Graphics adapter information http www asiliant com Radstone on the world wide web is available at...

Page 16: ...4 bit 66 MHz PCI interface slots PCI IEEE P1386 1 provides an industry standard high speed 528 Mbytes second local expansion bus designed for graphics high speed communications e g ATM FDDI ISDN etc multi media and user defined custom functions PCI has established itself as the leading local interconnect standard and the wide availability of compatible devices coupled with its adoption on an array...

Page 17: ...double width PMCs Optional PCI expansion bridge on a short PMC card and PMC carrier cards future proof your system design by enabling PCI sub system expansion to add new low cost interface capability as required Two on board Ethernet controllers giving 10 100BaseT Radstone COTS software support includes BIT Boot firmware BSPs and ESPs with BCS for LynxOS LynxOS HA VxWorks Tornado and RTEMS Wide ra...

Page 18: ... use of industry standard components and buses and a wide range of operating systems As well as providing a detailed hardware design specification the PowerPC Platform also embodies a software mechanism that allows the hardware to be isolated from the application by abstraction layers It is these abstraction layers in effect very low level system drivers that are the key to differentiation scalabi...

Page 19: ...PECFP95 7455 733 32 1 23 9 PowerPC 7410 The PowerPC 7410 is a 32 bit superscalar RISC processor clocked at 500 MHz and above with the following features 64 bit external data bus On chip 32 Kbyte instruction and data caches Enhanced branch prediction capabilities MMU and integral FPU On chip L2 cache controller that connects to a private L2 cache bus operating at up to 200 MHz The PowerPC 7410 impl...

Page 20: ...optional mezzanine expansion modules PMCs The PCI mezzanine format also provides 64 I O pins for user definition A range of PMCs are available from Radstone including high performance graphics MIL STD 1553 asynchronous serial Fast Ethernet FLASH memory Fibre Channel and ATM all fully compliant with the IEEE P1386 1 standard Using the PCI to PCI bridge device on the PMCPCI bridge card see overleaf ...

Page 21: ...h is the left most slot of the P0 PCI backplane For further information about P0 backplanes please contact Radstone directly or talk to your nearest Sales Office Memory System RAM Between 64 and 512 Mbytes using 256 Mbit devices of system memory is available The SDRAM is configured as two banks with the GT64260 directly controlling both The GT64260 data protection is by two methods Error Correctio...

Page 22: ...nts general purpose I O and auxiliary functions are implemented through an South bridge bus interface Facilities provided include Parallel printer port Four PC compatible serial interfaces Floppy disk controller Real time clock Keyboard mouse interface USB Input Output The PPC7A has a wide variety of possible I O connectivity including the following ports Ultra SCSI Ethernet Serial Mouse keyboard ...

Page 23: ...g VxWorks bootroms the Boot firmware technology is absorbed into such boot methodology Built In Test PPC BIT probes from the lowest level of discrete on board hardware up to Line Replaceable Unit level within a system ensuring the highest degree of confidence in system integrity BIT includes comprehensive configuration facilities allowing automatic initialisation tests to be defined for the desire...

Page 24: ...proach allows users to implement a verifiable BSP standard and yet not be locked out of using valuable extra features which will adapt the BSP but shorten development times ESP features may be added or removed as desired during development Typical features include VME DMA for VxWorks not included in WindRiver s BSP definition and VME enhancements like dynamic windowing and interrupt generation for...

Page 25: ...d features wide temperature range industrial grade devices an integral thermal management layer and incorporates a central stiffening bar for additional strength Cooling is achieved through conduction of heat from the thermal management layer to the cold wall of the rack to which the boards are secured by screw driven wedgelocks Level 4 boards are 100 temperature characterized and conformally coat...

Page 26: ...ts are identified by labels at strategic positions You can cross check these against the Advice Note provided as a separate note with your delivery On the outside of the shipping box and the antistatic bag there is a label similar to the following On the card within the antistatic bag there is an identifying label similar to the following attached to the printed wiring board This is fitted in the ...

Page 27: ... is also attached to the printed wiring board The Ethernet number has the form XX XX XX XX XX XX for instance 00 80 8E 00 50 93 Inspection 1 Visually inspect the board for any damage and loose or dislodged components 2 Report any defects you detect to Radstone 3 Referring to Chapter 4 Configuration visually inspect the board to ensure that the default configuration is correct and that there are no...

Page 28: ...onfiguration of links on the PPC7A The board is delivered with push on jumper links but for more rugged or military applications link pins must be connected using wire wraps Figure 4 1 Link Locations Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 29: ...in the following pages Note If you are about to install your board and power up for the first time leaving your board in the default configuration as above will enable board operation to be proved prior to tackling any more configuration issues RTC Standby Supply Voltage Link E1 This link selects the voltage of the standby supply to the I C RTC DS1337 As the normal VME standby voltage is 5 Volts t...

Page 30: ...r to program boot code to the FLASH devices To program the boot code into the FLASH devices the VME master will need to program up both the Universe and also the GT 64260 to allow a window from VME into the FLASH devices SETTING FUNCTION In VME programming mode Out default Normal boot mode Use of this link relies on the default Universe II configuration see the VMEbus Interface Configuration secti...

Page 31: ... of the links are fitted the PPC7A boots from the alternate boot image After boot time the link setting can be software overridden to select the different images E7 E8 FUNCTION Out default Out default Normal FLASH boot image operation Out In Alternate FLASH boot image In Out Recovery Boot image In In 2nd Alternate FLASH boot image Data area On board SCSI Terminator Enable Link E13 This link enable...

Page 32: ...re decoded as follows BOARD ID E10 E12 E2 E11 15 default Out Out Out Out 14 Out Out Out In 13 Out Out In Out 12 Out Out In In 11 Out In Out Out 10 Out In Out In 9 Out In In Out 8 Out In In In 7 In Out Out Out 6 In Out Out In 5 In Out In Out 4 In Out In In 3 In In Out Out 2 In In Out In 1 In In In Out 0 In In In In Links E11 E2 E12 and E10 are also connected to the VME64 GA0 to GA3 signals respecti...

Page 33: ...e 15 No E 0xE000 0000 None 16 No F 0xF000 0000 None Note Any change to the Board ID links will require the hardware registers to be relearned if BIT is not to fail VMEbus Interface Configuration Several operating features of the Universe II VME interface are set at power up or reset by surface mount jumper links All of these except local register access may be overridden by software The default se...

Page 34: ...e following table shows the function of the connectors on the PPC7A CONNECTOR FUNCTION P1 VMEbus P2 VMEbus P0 PMC site 1 I O J11 J12 J14 PMC site 1 J21 J22 J24 PMC site 2 J25 J26 I O expansion P8 RISCWatch P10 JTAG Factory use Figure 5 1 Connector Positions Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 35: ...12 GND DS1 BR0 SYSRESET NC 13 NC DS0 BR1 LWORD GA2 14 GND WRITE BR2 AM5 NC 15 NC GND BR3 A23 GA3 16 GND DTACK AM0 A22 NC 17 NC GND AM1 A21 GA4 18 GND AS AM2 A20 NC 19 NC GND AM3 A19 NC 20 GND IACK GND A18 NC 21 NC IACKIN NC A17 NC 22 GND IACKOUT NC A16 NC 23 NC AM4 GND A15 NC 24 GND A07 IRQ7 A14 NC 25 NC A06 IRQ6 A13 NC 26 GND A05 IRQ5 A12 NC 27 NC A04 IRQ4 A11 NC 28 GND A03 IRQ3 A10 NC 29 NC A02 ...

Page 36: ..._A RST SCSI 5V GPIO5 COM5_RXD 14 GND MSG SCSI D16 GPIO6 COM5_CTS 15 COM4_RXD_B SEL SCSI D17 GPIO7 COM3_TT_A 16 GND C D SCSI D18 GPIO8 COM3_TT_B 17 COM4_CTS_A REQ SCSI D19 GPIO9 COM3_ST_A 18 GND I O SCSI D20 GPIO10 COM3_ST_B 19 COM4_CTS_B TERMPWR SCSI D21 GPIO11 COM3_RT_A 20 GND USBP0 MOUSE_CLK D22 GPIO12 COM3_RT_B 21 N C USBP0 MOUSE_DATA D23 GPIO13 COM4_RTS_A 22 GND KBD_5V GND GPIO14 COM4_RTS_B 23...

Page 37: ..._IO_19 14 GND MSG SCSI D16 GPIO6 PMC2_IO_21 15 PMC2_IO_23 SEL SCSI D17 GPIO7 PMC2_IO_22 16 GND C D SCSI D18 GPIO8 PMC2_IO_24 17 PMC2_IO_26 REQ SCSI D19 GPIO9 PMC2_IO_25 18 GND I O SCSI D20 GPIO10 PMC2_IO_27 19 PMC2_IO_29 TERMPWR SCSI D21 GPIO11 PMC2_IO_28 20 GND USBP0 MOUSE_CLK D22 GPIO12 PMC2_IO_30 21 PMC2_IO_32 USBP0 MOUSE_DATA D23 GPIO13 PMC2_IO_31 22 GND KBD_5V GND GPIO14 PMC2_IO_33 23 PMC2_IO...

Page 38: ...SY 19 GPIO11 WPROT PERROR 20 GPIO12 TRK0 SELECT 21 GPIO13 INDEX AUTOFD 22 GPIO14 DENSEL ERR 23 GPIO16 GPIO16 ACGAME3 INIT 24 GPIO17 GPIO17 ACGAME4 SLCTIN Notes There is no connection to GPIO15 of the south bridge from the P2 connector There are three build options on these pins GPIO and Floppy standard LPT parallel port GPIO or Floppy section is via software control of the south bridge Build optio...

Page 39: ...s to use the bus D00 to D31 Data Bus These are used to transfer data between masters and slaves and status ID information from interrupters to interrupt handlers DS0 DS1 Data Strobe 0 1 These are used with LWORD and A01 to show how many byte locations are being accessed 1 2 3 or 4 Also during a write cycle the falling edge of the first data strobe shows that valid data is available on the bus On a...

Page 40: ...tor power Supplies power for external SCSI bus terminators Rated at 1 Amp MOUSE_CLK Mouse Clock Clock drive for mouse MOUSE_DATA Mouse Data Mouse data line KBD_5V Keyboard 5V Supplies power for the keyboard and mouse or USB supply when USB is fitted Rated at 1A KBD_CLK Keyboard Clock Clock drive for the keyboard KBD_DATA Keyboard Data Keyboard data line COM1 2 3 4 5 6_TXD COM1 2 3 4 5 6 Transmit D...

Page 41: ...WREN Global FLASH write enable EXT_RESET External Reset Hard Reset EXT_ABORT External Abort Soft Reset USBP0 USBP0 USB interface Port 0 USBP1 USBP1 USB interface Port 1 RED GREEN BLUE VSYNC HSYNC VGA port PMC2_IO_1 to PMC2_IO_46 I O signals from PMC site 2 This is a resettable fuse The fuse rating is the current rating that the fuse can carry In 20 C still air the fuse trips at twice the rated cur...

Page 42: ... GND 11 PMC2_IO_52 PMC2_IO_51 PMC2_IO_61 PMC2_IO_58 PMC2_IO_57 GND 12 PMC1_IO_30 PMC1_IO_29 PMC1_IO_28 PMC1_IO_27 PMC1_IO_26 GND 13 PMC1_IO_35 PMC1_IO_34 PMC1_IO_33 PMC1_IO_32 PMC1_IO_31 GND 14 PMC1_IO_40 PMC1_IO_39 PMC1_IO_38 PMC1_IO_37 PMC1_IO_36 GND 15 PMC1_IO_45 PMC1_IO_44 PMC1_IO_43 PMC1_IO_42 PMC1_IO_41 GND 16 PMC1_IO_50 PMC1_IO_49 PMC1_IO_48 PMC1_IO_47 PMC1_IO_46 GND 17 PMC1_IO_55 PMC1_IO_5...

Page 43: ...IO_26 GND 10 PMC1_IO_35 PMC1_IO_34 PMC1_IO_33 PMC1_IO_32 PMC1_IO_31 GND 11 PMC1_IO_40 PMC1_IO_39 PMC1_IO_38 PMC1_IO_37 PMC1_IO_36 GND 12 PMC1_IO_45 PMC1_IO_44 PMC1_IO_43 PMC1_IO_42 PMC1_IO_41 GND 13 PMC1_IO_50 PMC1_IO_49 PMC1_IO_48 PMC1_IO_47 PMC1_IO_46 GND 14 PMC1_IO_55 PMC1_IO_54 PMC1_IO_53 PMC1_IO_52 PMC1_IO_51 GND 15 PMC1_IO_60 PMC1_IO_59 PMC1_IO_58 PMC1_IO_57 PMC1_IO_56 GND 16 5V PMC1_IO_64 P...

Page 44: ...enerates a Soft Reset See the Resetting the PPC7A section in Chapter 8 for more details NC No connection TCE6 TCE7 GT 64260 Timer counter enable TCT6 TCT7 GT 64260 Timer counter terminal count 3 3V These pins are not connected to a 3 3V supply 5V 5 Volts DC power PMC1_IO_1 to PMC2_IO_64 I O signals from PMC site 1 PMC2_IO_48 to PMC_IO_52 PMC2_IO_55 to PMC_IO_58 and PMC2_IO_61 to PMC_IO_64 I O sign...

Page 45: ...D 10 NC 11 GND 12 NC 13 CLK 14 GND 15 GND 16 GNTA 17 REQA 18 5V 19 VIO 20 AD31 21 AD28 22 AD27 23 AD25 24 GND 25 GND 26 C BE3 27 AD22 28 AD21 29 AD19 30 5V 31 VIO 32 AD17 33 FRAME 34 GND 35 GND 36 IRDY 37 DEVSEL 38 5V 39 GND 40 LOCK 41 NC 42 NC 43 PAR 44 GND 45 VIO 46 AD15 47 AD12 48 AD11 49 AD09 50 5V 51 GND 52 C BE0 53 AD06 54 AD05 55 AD04 56 GND 57 VIO 58 AD03 59 AD02 60 AD01 61 AD00 62 5V 63 G...

Page 46: ...29 AD18 30 GND 31 AD16 32 C BE2 33 GND 34 IDSELB 35 TRDY 36 3 3V 37 GND 38 STOP 39 PERR 40 GND 41 3 3V 42 SERR 43 C BE1 44 GND 45 AD14 46 AD13 47 M66EN 48 AD10 49 AD08 50 3 3V 51 AD07 52 REQB 53 3 3V 54 GNTB 55 NC 56 GND 57 NC 58 NC 59 GND 60 NC 61 ACK64 62 3 3V 63 GND 64 NC The 3 3V pins are connected to the PPC7A main 3 3V supply CAUTION Do not fit a PMC that requires more than 8 watts from the ...

Page 47: ...2 AD56 23 AD55 24 AD54 25 AD53 26 GND 27 GND 28 AD52 29 AD51 30 AD50 31 AD49 32 GND 33 GND 34 AD48 35 AD47 36 AD46 37 AD45 38 GND 39 V I 0 40 AD44 41 AD43 42 AD42 43 AD41 44 GND 45 GND 46 AD40 47 AD39 48 AD38 49 AD37 50 GND 51 GND 52 AD36 53 AD35 54 AD34 55 AD33 56 GND 57 V I O 58 AD32 59 Reserved PCI 60 Reserved PMC 61 Reserved PCI 62 GND 63 GND 64 Reserved PMC Artisan Technology Group Quality In...

Page 48: ...ST Reset Driven low to reset the PCI bus TRDY Target Ready Driven low by the current target to signal its ability to complete the current data phase PERR Parity Error Driven low by a PCI agent to signal a parity error SERR System Error Driven low by a PCI agent to signal a system error STOP STOP Driven low by a PCI target to signal a disconnect or target abort INTA to INTD Interrupt lines Level se...

Page 49: ...25 26 PMC1_IO_26 27 PMC1_IO_27 28 PMC1_IO_28 29 PMC1_IO_29 30 PMC1_IO_30 31 PMC1_IO_31 32 PMC1_IO_32 33 PMC1_IO_33 34 PMC1_IO_34 35 PMC1_IO_35 36 PMC1_IO_36 37 PMC1_IO_37 38 PMC1_IO_38 39 PMC1_IO_39 40 PMC1_IO_40 41 PMC1_IO_41 42 PMC1_IO_42 43 PMC1_IO_43 44 PMC1_IO_44 45 PMC1_IO_45 46 PMC1_IO_46 47 PMC1_IO_47 48 PMC1_IO_48 49 PMC1_IO_49 50 PMC1_IO_50 51 PMC1_IO_51 52 PMC1_IO_52 53 PMC1_IO_53 54 PM...

Page 50: ...IO_23 Z15 24 PMC2_IO_24 D16 25 PMC2_IO_25 D17 26 PMC2_IO_26 Z17 27 PMC2_IO_27 D18 28 PMC2_IO_28 D19 29 PMC2_IO_29 Z19 30 PMC2_IO_30 D20 31 PMC2_IO_31 D21 32 PMC2_IO_32 Z21 33 PMC2_IO_33 D22 34 PMC2_IO_34 D23 35 PMC2_IO_35 Z23 36 PMC2_IO_36 D24 37 PMC2_IO_37 D25 38 PMC2_IO_38 Z25 39 PMC2_IO_39 D26 40 PMC2_IO_40 D27 41 PMC2_IO_41 Z27 42 PMC2_IO_42 D28 43 PMC2_IO_43 D29 44 PMC2_IO_44 Z29 45 PMC2_IO_4...

Page 51: ...Connector Pinout P8 is the RISCWatch connector allowing the connection of software debugging tools that use the processor s JTAG port to control the operation of the processor PIN NO SIGNAL PIN NO SIGNAL 1 TDO_CPU 2 EMU QACK_IN 3 TDI_CPU 4 TRST 5 QREQ 6 3 3V pull up 7 TCK 8 NC 9 TMS 10 NC 11 SRESET_CPU 12 GND 13 HRESET_CPU 14 NC 15 CHECKSTOP 16 GND For more information on JTAG see Chapter 8 Artisa...

Page 52: ...et CHECKKSTOP Processor Checkstop output GND Signal ground For more information on JTAG see Chapter 8 EST Emulator Connection PIN NO SIGNAL DESCRIPTION 1 TDO_CPU Processor JTAG Test Data Out 2 QACK_IN Quiescent grant to Processor 3 TDI_CPU Processor JTAG Test Data In 4 TRST Processor JTAG Test Reset 5 QREQ Processor Quiescent request 6 3 3V pull up Power on status signal to EST hardware 7 TCK Proc...

Page 53: ... DS3 are mounted on the front panel DS1 is yellow DS2 is red and DS3 is green See the Software Programmable LEDs section in Chapter 9 for more details Switches A momentary action toggle switch is fitted to allow generation of a hard reset or abort With the board in the orientation as shown in Figure 6 1 moving the switch to the left causes an abort and moving the switch to the right causes a hard ...

Page 54: ...PPC7A Product Manual Front Panel 6 2 Figure 6 1 PPC7A Front Panel 1st Edition Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 55: ...HN4 3 99 contains the fitting instructions PMCs ordered with a PPC7A can be supplied factory fitted by Radstone if required It may be necessary to install driver software or implement other firmware configuration to achieve full functionality of a PMC see the specific PMC manual for the exact procedure Note You are recommended not to route analog signals through P0 The PMCPCI PCI expansion card sh...

Page 56: ...n The lower link configures the Interrupt Acknowledge IACK daisy chain When a slot position is not occupied by a board and there are boards further down the daisy chain connect the appropriate In signal BGxIN IACKIN at that slot to the corresponding Out signal BGxOUT IACKOUT at the same slot using these links Some backplanes have daisy chains that automatically link the signals across empty slots ...

Page 57: ... in the rack or enclosure Note The default link configuration requires the board to be inserted into system slot 1 2 Push the board firmly home to ensure the connectors mate properly with the backplane 3 Tighten the captive screws at the top and bottom of the front panel to secure the board in position Note Pulling on any front panel cable connections could inadvertently disconnect the board if it...

Page 58: ...o the PPC7A This terminal will use the serial signals on COM1 Cables supplied by Radstone permit direct connection to a terminal without use of a null modem Alternatively a PMC9100 PMC2 9100 graphics PMC and a USB or PS 2 compatible keyboard may be used If these devices are used the firmware detects their presence and uses them automatically Power up In preparation for power up ensure you have Con...

Page 59: ...gram BIT is described in the PPC BIT Release Notes publication number RT5111 The Boot firmware is described in the PPC Boot Firmware Manual publication number RT5078 VxWorks is described in the VxWorks BSP for PPCx Release Notes publication number RT5080 1st Edition Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 60: ...ded by the Operating System s Hardware Independence mechanism BSP HAL residual data etc and not directly by application software 3 If a standard operating system is not being used then it is recommended that applications are written in such a way as to minimize direct access to hardware resources bearing in mind that changes may be necessary to support future iterations of the hardware 4 Radstone ...

Page 61: ...n write through or write back modes Operation at speeds up to 266 MHz through a dedicated L3 cache bus interface Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 i e SDRAM Entries in write through mode can be valid or invalid Entries in write back mode can be invalid valid unmodified or valid modified Having the L3 cache controller inside the MPC7455 allows performance to...

Page 62: ...e back modes Operation at speeds up to 266 MHz through a dedicated L2 cache bus interface Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 i e SDRAM Entries in write through mode can be valid or invalid Entries in write back mode can be invalid valid unmodified or valid modified Having the L2 cache controller inside the MPC7410 allows performance to be further enhanced by...

Page 63: ...hard reset signal pin C1 Hard reset all devices If System Controller SW_LRST bit VCSR bit Hard reset excluding VMEbus Interface No Software Events SW_SYSRESET bit Hard reset if System Controller If System Controller The SW_LRST VCSR and SW_SYSRESET bits are located in the Universe II PCI VME bridge The front panel hard reset may be disabled under software control or by fitting hardware jumper E14 ...

Page 64: ...ft reset signal pin 11 Software Events HOT_RESET bit in ISA bridge The front panel soft reset switch may be disabled under software control or by fitting hardware jumper E14 The standard boot firmware does not support the use of soft reset VMEbus Remote Reset Another VME master may reset the PPC7A via the Universe II control registers This causes a hard reset Watchdog Reset If enabled and triggere...

Page 65: ... the size and number of banks of SDRAM and the appropriate number of wait states to match the SDRAM speed This is done by the standard Boot firmware The size of the SDRAM may be checked by reading the Memory Configuration register see the Control and Status Registers section At least 100µs must have elapsed from the negation of reset before enabling the SDRAM After being enabled the SDRAM must not...

Page 66: ...OT_ALTERNATE and E8 BOOT_RECOVERY links To write to this area Links E5 Overall FLASH Write Enable and E9 System FLASH Write Protected need to be fitted Alternate BOOT This area would normally contain a backup or alternate boot image This is useful when developing boot code to be able to switch between two images to check operation If an alternate boot image is not required this area can be used to...

Page 67: ... VME by default The VME master will use these registers to set up windows onto the PCI bus from VME The GT64260 will have its register set available at address 0x1400 0000 The PowerPC s boot FLASH can be accessed at address 0xFFF0 0000 on PCI These areas will need mapping onto VME to allow access of the FLASH memory For correct operation of the FLASH memory 0xF428 1278 should be written to the GT6...

Page 68: ...3V via a 4 7 kΩ pull up resistor TDI 3 3V via a 4 7 kΩ pull down resistor The JTAG signals from P8 connect into the CPU JTAG signals They have the following terminations TCK 3 3V via a 1 kΩ pull down resistor TMS 3 3V via a 10 kΩ pull up resistor TDI 3 3V via a 1 kΩ pull down resistor TRST 3 3V via a 1 kΩ pull up resistor The JTAG signals from J11 J12 PMC site connect into the MAIN JTAG signals on...

Page 69: ...e PPC7A has BUSMODE2 to BUSMODE4 wired to 1 0 0 respectively This effectively interrogates the PMC site as to whether it has a PCI compliant card fitted The response from the PMC is returned on BUSMODE1 If the answer is yes BUSMODE1 0 then the PMC site is included in the JTAG chain If there is no PMC fitted then a pull up resistor on the PPC7A forces BUSMODE1 to 1 and the JTAG is bypassed Notes 1 ...

Page 70: ...nted as a 64 bit PCI bus running at up to 66 MHz This gives a burst rate up to 528 Mbytes second between PCI agents The PCI bus structure of the PPC7A is shown below Memory PCI Bridge The Memory PCI Bridge on the PPC7A is provided by a Galileo GT64260 Discovery device This device provides Host Bridge between the processor bus and the two PCI buses SDRAM memory controller and FLASH interface see th...

Page 71: ...onously or 14 Mbytes second asynchronously Connection to the SCSI bus is made through the P2 connector The pinout is given in Chapter 5 The PPC7A has an on board active SCSI terminator which may be enabled or disabled with a jumper see the E13 description in Chapter 4 The SCSI specification allows a maximum cable stub length of 10 cm If the SCSI bus connections are taken directly from the backplan...

Page 72: ...ing a PMCPCI card allows the PCI bus to come out to the backplane via P0 must be fitted in PMC slot 1 South Bridge Peripheral Components The South Bridge connected to the PCIbus contains a floppy disk controller 16 bit digital IO two serial ports a parallel port and a keyboard mouse controller The IDE interface is not used on the PPC7A Floppy Disk Controller Connection to the FDC is through P2 Thi...

Page 73: ...local address to a different address on the VMEbus allowing any local address to access any VMEbus address The start and end addresses of the A32 A24 and A16 PCI slave images may be set on any 64 Kbyte boundary in PCI memory or I O space that is not allocated to other PCI attached devices or the user FLASH One image may be set on 4 Kbyte boundaries to accommodate access to A16 space One further sp...

Page 74: ...hold ownership of the VMEbus This method can be used in combination with VMEbus LOCK cycles to guarantee exclusive access to a VMEbus resource The VMEbus slave images may be programmed to generate locked cycles on the PCI bus to handle RMW cycles The Universe II chip also supports VMEbus lock commands using ADOH cycles VMEbus Arbitration The Universe II chip s VMEbus arbiter supports PRI and RRS a...

Page 75: ...nowledge cycle The Universe captures the status ID and then raises an interrupt on the PCI bus No further VMEbus interrupts are handled on that level until the processor reads the status ID and re arms the interrupt handler The Universe II can be programmed to generate any level of VMEbus interrupt It can raise an interrupt on the PCI bus when the VMEbus interrupt has been acknowledged Seven softw...

Page 76: ...See the VMEbus Interface Configuration section in Chapter 4 for the default options Watchdog Timers The PPC7A contains a Maxim 706 microprocessor supervisory circuit with a watchdog timer Once enabled this timer must be re triggered every 1 6 seconds or a hard reset results The trigger control registers is 0x82C and is enabled via Control register 0x828 Note Once this bit is enabled as an output s...

Page 77: ...e other 8 LEDs are all surface mounted on the back of the PCB DS16 DS17 DS18 and DS19 are Ethernet status LEDs for channel 1 and DS20 DS21 DS22 and DS23 are for channel 2 The default functions of these LEDs are link TX activity RX activity status and 100BaseT respectively but these may be overridden by the software The PPC7A has the following software programmable LEDs Figure 8 3 Position of LEDs ...

Page 78: ...Extended Mode WO 0410 to 043F South Bridge DMA Scatter Gather 0481 to 048B South Bridge DMA High Pages 04D0 and 04D1 South Bridge Edge Level Control 04D6 DMA 2 Extended Mode WO 0804 Memory Configuration RO 0806 Memory Configuration Extend RO 0808 SCSI Activity LED R W 080C Equipment Present 1 RO 080E Equipment Present 2 RO 0810 Equipment Present 3 RO 0818 Key Lock RO 0820 LEDS R W 0824 COMs R W 08...

Page 79: ...ing register descriptions the bit significance is shown in big endian mode i e from the viewpoint of the PowerPC 750 programmer Memory Configuration Register Port 0x0804 This register provides information on the SDRAM fitted MSB D0 LSB D7 D0 Memory type 1 SDRAM D1 NVRAM type 0 FRAM 1 NVSRAM D2 to D4 Reserved always read as 1 D5 Reserved always read as 0 D6 SDRAM Bank 1 Fitted 0 Fitted 1 Not fitted...

Page 80: ...ize 0 64 Mbytes 1 128 Mbytes 2 256 Mbytes 3 Reserved D2 to D4 Reserved D5 to D7 FLASH banks and size configuration D5 D6 D7 DEVICE SIZE NO OF BANKS MBYTES 0 0 0 256 M bit 1 128 0 0 1 128 M bit 1 64 0 1 0 Reserved 1 Reserved 0 1 1 64 M bit 1 32 1 0 0 256 M bit 2 256 1 0 1 128 M bit 2 128 1 1 0 Reserved 2 Reserved 1 1 1 64 M bit 2 64 Artisan Technology Group Quality Instrumentation Guaranteed 888 88...

Page 81: ...r power fuse MSB D0 LSB D7 D0 Hardware ID0 see the Motherboard Type Register for details D1 SCSI_FUSE_GOOD 0 SCSI fuse bad 1 SCSI fuse good Note This is a re settable fuse that re engages when the overcurrent condition is removed D2 PRSNT1_2 0 Slot 2 PMC present 1 Slot 2 empty D3 PRSNT1_1 0 Slot 1 PMC present 1 Slot 1 empty D4 PCI1 bus speed 0 33 Mhz 1 66 Mhz D5 and D6 Cache Size D5 SIZE1 D6 SIZE0...

Page 82: ...e II Fitted 0 Not fitted 1 Fitted D1 Reserved always reads 0 D2 COMs 3 to 6 Fitted 0 Not fitted 1 Fitted D3 USB Fitted 0 Not fitted 1 Fitted D4 LPT Fitted 0 Not fitted 1 Fitted D5 and D6 Cache Speed D5 D6 SPEED MHZ 0 0 Reserved 0 1 Reserved 1 0 200 1 1 166 D7 Cache Type 1 Double data rate 0 Standard data rate Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg c...

Page 83: ... Powered by onboard power supply 1 Power from taken from 3 3V pins on VME connectors D6 and D7 SCSI clock speed D6 D7 SPEED MHZ 0 0 Reserved 0 1 40 1 0 80 1 1 Reserved Key Lock Register Port 0x0818 This register provides information on the state of the keylock signal See the Keylock section for more details MSB D0 LSB D7 D0 to D6 Reserved D7 Keylock 0 Keylock signal low 1 Keylock signal high Artis...

Page 84: ...is 8Kbytes D4 DS11 yellow 0 LED off OFFLINE High 1 LED on OFFLINE Low D5 DS13 and DS1 Yellow 0 LED on SYSFAIL Low 1 LED off SYSFAIL High D6 DS12 and DS2 Red and S YSFAIL P0 B1 signal 0 LED off 1 LED on D7 DS14 and DS3 Green and SYSFAIL P0 B2 signal 0 LED off 1 LED on See the Software Programmable LEDs section and Chapter 6 for the location of these LEDs Note DS12 and DS2 are on by default after po...

Page 85: ...32 selects which interface is used for COM3 0 RS232 1 RS422 D3 COM3_TX_EN when enabled allows all of the COM3 interface buffers 0 Disabled 1 Enabled D4 COM4_CLK_EN this bit enables the TSCLK4 signal out on to COM4_TT transmit clock 0 Disabled 1 Enabled D5 TSCLK4_EN when enabled COM4_RT receive transmit clock is linked to TSCLK4 is 0 Disabled 1 Enabled D6 COM4_RS232 selects which interface is used ...

Page 86: ...g Register Port 0x0828 This register controls the watchdog resets features of the PPC7A MSB D0 LSB D7 D0 Last reset was a watchdog 0 Normal reset 1 Last board reset was caused by a watchdog timeout D1 Enable NMI from GT 64260 0 Disabled 1 NMI can be generated from GT 64260 CPUINT output pin D2 to D5 Reserved Reads 0 D6 Watchdog enable 0 Trig output disabled 1 Trig output enabled Once the trig outp...

Page 87: ...MSB D0 LSB D7 D0 to D2 Number revision of hardware build state 1 Revision 1 2 Revision 2 3 Revision 3 All other values are Reserved D3 to D7 Letter revision of hardware build state 0x0 Revision A 0x1 Revision B 0x18 Revision Y 0x19 Revision YA 0x1F Revision YG Extended ID Register Port 0x0858 This register provides Board hardware type MSB D0 LSB D7 D0 to D7 Board ID register 0x0E PPC7A 7410 755 0x...

Page 88: ... 0 Link fitted 1 Link not fitted D5 E10 GA2 0 Link fitted 1 Link not fitted D6 E8 GA1 0 Link fitted 1 Link not fitted D7 E4 GA0 0 Link fitted 1 Link not fitted Note Bits D4 D5 D6 and D7 are also connected to the VME64 Geographical Address bits GA3 GA2 GA1 and GA0 respectively Do not fit the links if you wish to read the status of the Geographical Address bits as the links connect these bits to 0 V...

Page 89: ..._TYPE 0 Reserved 1 ECC D3 ECC 0 ECC not fitted 1 ECC fitted D4 PLL1 see table below D5 PLL0 see table below PLL2 PLL1 PLL0 BUS SPEED MHZ 1 1 1 Reserved 1 1 0 Reserved 1 0 1 Reserved 1 0 0 133 0 1 1 Reserved 0 1 0 100 0 0 1 66 0 0 0 Reserved D6 and D7 Hardware ID2 and ID1 respectively Used with Hardware ID0 bit 0 of Equipment Present Register 1 to define the hardware type as follows ID2 TO ID0 HARD...

Page 90: ..._WREN signal 0 Signal not active Pin high 1 Signal active Pin low D2 FLASH BOOT write enable link 0 link not fitted 1 link fitted D3 FLASH USER write enable link 0 link not fitted 1 link fitted D4 Always reads 0 D5 Writes to FLASH recovery section 0 Disabled 1 Enabled D6 Writes to FLASH BOOT section 0 Disabled 1 Enabled D7 Writes to FLASH USER section 0 Disabled 1 Enabled Artisan Technology Group ...

Page 91: ... selected MSB D0 LSB D7 D0 NVRAM Write Protect 0 NVRAM is write protected 1 Writes to NVRAM are enabled D1 BOOT_ALTERNATE reflects the status of user link E8 This bit is read only 0 Link not fitted 1 Link fitted D2 VME_BOOT_MODE reflects the status of user link E4 This bit is read only 0 Link not fitted 1 Link fitted D3 BOOT_RECOVERY reflects the status of user link E7 This bit is read only 0 Link...

Page 92: ...5 0x0F PPC7A 745x 0x10 PPC7FW MPC7410 with Firewire All others patterns mean the board is not a PPC7A Last Reset Source Port 0x2 This register provides information about what caused the last reset MSB D0 LSB D7 D0 to D2 Reserved D3 GT64260 watchdog timed out 0 Did not cause the last reset 1 Caused the last reset D4 MAX706 Watchdog Timed out 0 Did not cause the last reset 1 Caused the last reset D5...

Page 93: ...t 0x6 MSB D0 LSB D7 D0 to D7 Reads 0x43 C Port 0x7 MSB D0 LSB D7 D0 to D7 Reads 0x37 7 Status Registers on CS1 These registers are accessed via the GT64260 CS1 address window see GT64260 for more information for setting up this address window CS0 I O PORT HEX DESCRIPTION TYPE 0000 to 0003 Checker board 1 RO 0004 to 0007 Checker board 2 RO Where RO Read Only Checker Board 1 Port 0x0 to 0x3 This reg...

Page 94: ...apter Machine Check Exception The South Bridge can be configured the signal NMI on certain conditions The hardware on the PPC7A routes this signal to the CPU as the MCP Machine Check interrupt The South Bridge can drive this signal due to the following conditions PCI bus error PCI SERR signal driven active The PCI SERR signal can be driven low by other PCI devices to report a error condition The p...

Page 95: ... carrier These are connected to the PIRQ inputs of the interrupt controller The PIRQ inputs may be routed to any IRQ that is set to level sensitive mode The interrupt routing follows the recommendations in the PCI specification and the PCI system design guide with a rotation between each slot The interrupt lines for the two on board PMC slots are routed as shown below Two single function PMCs whic...

Page 96: ...e device number mapping for the PCI bus 0 attached to the GT64260 is as follows DEVICE NO FUNCTION 0 to 15 Not implemented 16 53C860 SCSI controller 17 Not implemented 18 South bridge 19 Not implemented 20 Universe II VME controller 21 Graphics 22 to 30 Not implemented The device number mapping for the PCI bus is as follows DEVICE NUMBER FUNCTION 0 TO 22 Not implemented 23 PMC2 24 PMC1 25 TO 30 No...

Page 97: ... you may also register support requests using the Technical Support Request Form available through the Radstone web site at http www radstone co uk This form looks like Your query will be logged on Radstone s Technical Support database and allocated a unique Call Reference Number CRN for use in future correspondence If you telephone for technical support please be prepared to provide the above det...

Page 98: ...eck that the cable stub length is less than 10 cm You are also recommended to locate the PPC7A at one end and enable the bus terminator by fitting link E13 If you want to use the PPC7A somewhere other than at the end of the SCSI bus ensure that E13 is not fitted Fitting E13 when the PPC7A is not located at the end of a SCSI bus may cause erroneous SCSI operation If you have made your own cable for...

Page 99: ...nce Local resources EMC regulatory compliance and safety Power requirements Reliability Mean Time Between Failures Environmental specifications for both build levels General dimensions Weight Ordering Information and options in o Board o Firmware o Operating Systems o PMCs o P2 I O Modules Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 100: ...EO BLT D16 D16 RMW D16 BLT D32 D32 RMW D32 BLT D32 UAT D64 MBLT Interrupt Handler D08 O IH 1 7 Interrupter I 1 7 VMEbus Arbiter SGL RRS PRI BCLR generation VMEbus Requester ROR RWD Early BBSY release Bus capture and hold Bus Time out Module 16 32 64 128 256 512 1024 µS disabled Other Slot 1 Functions Slot 1 detector IACK daisy chain driver SYSCLK driver Auto Slot ID VME64 specified and SCV64 compa...

Page 101: ...64 bit 66 MHz SCSI 8 bit fast Ultra SCSI via the P2 connector Ethernet 2 off Ethernet 10 100BaseT via the P2 connector PMC Slots Air cooled Two 5V 32 bit IEEE P1386 1 compliant slots with front panel and P0 I O and restricted P2 I O Serial I O Six serial I O channels via the P2 connector Two channels are equipped with clocks for synchronised operation with interfaces that allow for RS422 or RS232 ...

Page 102: ...of 3500 mA for the 128 Mbyte SDRAM version and 3500 mA for the 256 Mbyte SDRAM version Note When using PMCs ensure that they do not cause the specified maximum supply current to be exceeded especially from the 5V supply The VME specification allows a maximum of 7 5 Amps to be drawn from the 5V supply in a single slot over the PPC7A s specified operating temperature range It may not be possible to ...

Page 103: ...fitted PMCs The failure rates used in this calculation are based on MIL HDBK 217F Notice 1 parts count method with commercial or non military quality level Where a component did not comply with the MIL HDBK the closest equivalent compliant component was used Environmental Specifications BUILD STYLE OPERATING TEMP C STORAGE TEMP C VIBRATION SHOCK HUMIDITY COMMENTS Standard level 1 0 to 55 with airf...

Page 104: ...sions The PPC7A is constructed on a multi layer double Eurocard and conforms to the dimensions specified in the ANSI VITA 1 1994 specification The dimensions shown below are in millimetres with inches in parentheses for general guidance only Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 105: ...d Mouse GPIO 6 128MB USB Parallel 7 128MB Keyboard Mouse Parallel 8 256MB USB GPIO 9 256MB Keyboard Mouse GPIO A 256MB USB Parallel B 256MB Keyboard Mouse Parallel MEMORY 0 Reserved 1 128MB 2 3 Reserved 4 256MB X 5 512MB PROCESSOR 0 to 4 Reserved 5 755 400MHz 6 to 9 Reserved A B Reserved X C 7410 500MHz LEVEL 1 2 3 4 5 PROCESSOR 7410 Notes P0 options are available on all build levels Due to the la...

Page 106: ...2 options PMCEXT Ethernet interface 1 and 2 only 100BaseTX Fast Ethernet interface PMCATMF ATM interface 1 to 4 155 Mbps ATM adapter for OC 3 fiber networks PMCF1 FLASH memory 1 to 5 High capacity FLASH 32 64 96 or 128 Mbytes options PMCF2 Compact FLASH 1 to 5 Solid state hard disk using 40 Mbyte Compact FLASH Card PMCFA1 Fibrechannel interface 1 to 5 1 Gbit second full duplex Fibrechannel adapter...

Page 107: ...he Backplane Transition Module for the PPC7A is the P25X606 illustrated below Compatible Rear I O modules are shown in parenthesise For installation instructions refer to the I O Module Installation Guide Publication Number RT5154 Pin assignments and ordering information are given overleaf Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 108: ...UT P5 Parallel Keyboard Mouse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND RED GREEN BLUE HSYNC VSYNC J3 Analogue Monitor GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SCSI_DB0 SCSI_DB1 SCSI_DB2 SCSI_DB3 SCSI_DB4 SCSI_DB5 SCSI_DB6 SCSI_DB7 SCSI_DBP SCSI_TERMPWR SCSI_ATN SCSI_BSY SCSI_ACK SCSI_RST SCSI...

Page 109: ...ed COM4 terminated Ethernet Options 1 1 x Ethernet 2 2 x Ethernet Video Comms Options 1 Video COM 1 2 5 RS232 COM3 RS232 422 No COM6 2 No Video COM 1 2 5 6 RS232 COM 3 4 RS232 422 Build Level 1 Level 1 2 Levels 2 3 4 5 Note Where second Ethernet and Video connectors are not fitted a QXP2IO may be connected For details of this and other compatible I O modules refer to the I O Module Installation Gu...

Page 110: ...RT5116 BCS Background Condition Screening CR CSR Configuration ROM Control and Status Register LRU Line Replaceable Unit PPC7A Radstone s PowerPC based processor card The PPC7A is based on the PowerPC 745x 7410 processor with integral L3 L2 cache controller and uses SDRAM Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 111: ...1 3 E ECC 8 6 8 30 EMC 7 3 Regulatory Compliance A 4 Environment A 5 EST Emulator Connection 5 19 Ethernet Controller 8 12 F Floppy Disk Controller 8 13 Front Panel 6 1 Functional Overview 2 3 H Heatsink 1 5 I I O Capabilities 2 7 I O Modules A 9 Inspection 3 2 Installation Board 7 2 7 4 PMCPCI 7 1 Interrupts 8 35 External 8 36 Handling A 2 Interrupter A 2 PCI 8 36 SMI 8 35 VMEbus 8 16 Introductio...

Page 112: ... 8 5 Watchdog 8 5 Revision State 8 28 S Safety A 4 Notices 1 4 SCSI Processor 8 12 Terminator 8 12 8 22 9 2 Semaphores 8 16 Serial I O 8 13 Software Support 2 8 System Controller 8 14 T Technical Help 9 1 Telephone Number 9 1 U Universe II Chip 8 14 V VMEbus 7 2 Arbitration 8 15 Booting 8 8 Bus Errors 8 16 Compliance A 2 Indivisible Cycles 8 15 Interface 2 7 Location Monitor 8 16 Master Access 8 1...

Page 113: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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