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EPC-5A Hardware & Software Reference Manual

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Parallel Port

The DB-25 LPT1 parallel port connector is an Output-Only device defined as:

Pin Signal

1 Strobe

14 Auto line feed

2 DB0

15 Error

3 DB1

16 Initialize printer

4 DB2

17 Select in

5 DB3

18 Signal ground

6 DB4

19 Signal ground

7 DB5

20 Signal ground

8 DB6

21 Signal ground

9 DB7

22 Signal ground

10 Acknowledge

23 Signal ground

11 Busy

24 Signal ground

12 Paper end

25 Signal ground

13 Select

Table 7-2. Parallel Port Pinout.

Keyboard

The keyboard connector is a 6-pin DIN defined as:

Pin Signal

1 Data

4 +5V

2 not used

5 Clock

3 Ground

6 not used

Table 7-3. Keyboard Connector Pinout.

Summary of Contents for EPC-5A

Page 1: ...______________________________________ 07 0870 01 October 1998 EPC 5A Hardware Software Reference Manual RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro Oregon 97124 Phone 503 615 1100 Fax 503 615 1150 http www radisys com ...

Page 2: ...gistered trademarks of RadiSys Corporation Spirit DAI DAQ ASM Brahma and SAIB are trademarks of RadiSys Corporation All other trademarks registered trademarks service marks and trade names are the property of their respective owners October 1998 Copyright 1998 by RadiSys Corporation All rights reserved ...

Page 3: ...on of memory arrays or other devices may void the warranty and if the product is damaged during installation of the modifications this warranty does not cover repair or replacement This warranty in no way warrants suitability of the product for any specific application IN NO EVENT WILL RADISYS BE LIABLE FOR ANY DAMAGES INCLUDING LOST PROFITS LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGE...

Page 4: ...5 Subplane Installation 15 EXP BP2 Subplane 16 EXP BP4 Subplane 17 EXP BP3A Subplane 18 EXP BP5 Subplane 19 EXP BP4A Subplane 20 EXP BP6 Subplane 21 EPC 5A Insertion 22 EXP MC Module Carrier Insertion 23 EXP MX Mass Storage Module Insertion 24 EXM Module Insertion 24 Connecting Peripherals to the EPC 5A 25 Monitor 25 Keyboard 25 Serial Ports 26 Parallel Printer Port 26 EXP MX Ports 26 4 BIOS Confi...

Page 5: ... 53 Resetting the EPC 5A 54 EXM Expansion Interface 54 6 The VMEbus Interface 57 Connectivity 57 VMEbus System Slot 1 Controller Functions 57 Concepts 58 Memory Map 58 Direct VMEbus Accesses 59 Byte Ordering 60 Slave Accesses from the VMEbus 63 Self Accesses Across the VMEbus 64 Read Modify Write Operations 64 VMEbus Interrupt Response 65 Registers Specific to the EPC 5A 66 VMEbus Mapped Registers...

Page 6: ...ervice 107 In North America 107 Technical Support 107 World Wide Web 107 Repair Services 108 Warranty Repairs 108 Non Warranty Services 108 Arranging Service 109 Other Countries 110 Appendix A Chip Set I O Map A 1 Appendix B Interrupts and DMA Channels B 1 Interrupts B 1 DMA Channels B 2 Appendix C Flash Boot Device C 1 Flash Boot Device Reflashing C 3 Reflashing using REFLASH EXE C 6 User BIOS Ex...

Page 7: ... 7 EXP MC Module Carrier side view 23 Figure 4 1 BIOS Setup Menu Map 28 Figure 4 2 Main BIOS Setup Menu 29 Figure 4 3 IDE Adapter Sub menu 31 Figure 4 4 Memory Shadow Menu 33 Figure 4 5 Boot Options Sub Menu 34 Figure 4 6 Keyboard Features Sub menu 36 Figure 4 7 Advanced Menu 37 Figure 4 8 EXM Menu 39 Figure 4 9 Slot Numbering 40 Figure 4 10 VME Setup Menu 42 Figure 4 11 Exit Menu 44 Figure 6 1 So...

Page 8: ...ct Mapping 59 Table 7 1 Serial Port Pinout 87 Table 7 2 Parallel Port Pinout 88 Table 7 3 Keyboard Connector Pinout 88 Table 7 4 Speaker Header Pinout 89 Table 7 5 Battery Header Pinout 89 Table 9 1 Phoenix NuBIOS Checkpoint Codes 104 Table 9 2 Phoenix NuBIOS Auxiliary Checkpoint Codes 105 Table 9 3 Phoenix NuBIOS Boot Block Checkpoint Codes 105 Table B 1 Interrupts B 1 Table B 2 DMA Channels B 2 ...

Page 9: ...ropriate EPConnect VME manual The information in this manual is organized into the following sections Front Matter Warranty Information Table of Contents List of Figures and Tables Chapter 1 Product Description Provides an introduction to the EPC 5A a brief description of the features provided and a table of specifications Chapter 2 Before Installation Covers the details of configuring the EPC 5A ...

Page 10: ...echnical Support Appendix A Chipset and I O Map Appendix B Interrupts and DMA Channels Appendix C Flash Boot Device Appendix D Pformat For use with EXM 2A Appendix G Glossary A guide to terminology and acronyms used in this manual Notational Conventions The following notational conventions are used throughout this manual FFh Hexadecimal numbers are indicated by an h suffix In signal definitions th...

Page 11: ...ides direct communication to all three VMEbus address spaces A32 A24 A16 The EPC 5A DRAM permits dual ported access from both the PC side and the VME side The EXM expansion interface is electrically similar to the 16 bit PC AT ISA bus Video is provided through an add in card called an EXM EXpansion Module Mass storage can be added via the EXP MX Mass Storage module inside the VME chassis or extern...

Page 12: ... and EPC 5A The EPC 5A differs from the EPC 5 in the following ways 1 The System BIOS is based on Phoenix Technologies NuBIOS revision 4 05 The EPC 5 uses an Award BIOS 2 The EXP MS SCSI module is not supported 3 BIOS setup configuration is available only during the boot sequence it is not available after the OS boots The CTRL ALT ESC key sequence no longer invokes setup 4 The EPC 5A supports CMOS...

Page 13: ...arger than 528MB capacity 8 The Flash File System can be installed as a DOS device driver therefore flash can be installed as the second drive even when SCSI is the boot device EXM 16 9 IRQ 12 is only available to the EXMBus as a build time option 10 Slave memory is mapped to the VME bus in the following increments 2MB 4MB 8MB 10MB 16MB 32MB 64MB However system memory increments are no longer rest...

Page 14: ...EPC 5A Hardware Software Reference Manual Page 6 1 1 NOTES ...

Page 15: ...eakdown in semiconductor devices that might not result in immediate failure Configuring the EPC 5A The EPC 5A can be user configured to provide standard VMEbus Slot 1 functionality The Slot 1 configuration option is enabled default by installing the Slot 1 shunt jumper on the processor board see Figure 1 page 4 Removing the jumper disables Slot 1 functionality When the EPC 5A is configured as the ...

Page 16: ...SB backplane or Pin 30 Row A is defined for another purpose remove this jumper Selecting the EPC 5A Slot Location There are two main considerations in determining where the EPC 5A should be positioned in the chassis When used as a Slot 1 controller and per the VMEbus specification Rule 3 3 a Slot 1 controller must be in Slot 1 All other boards must be to the right of the Slot 1 controller The EPC ...

Page 17: ...r particular subsystem configuration requires Product VME Slots Total EPC 5A Includes first two EXM modules 2 Additional EXP MC s Holds additional two EXM modules 1 each EXP AM 2 Mass Storage Module EXP MX including EXP MX200A and greater 2 or EXP MX200 3 Total VMEbus slots used Table 2 1 VME Slots Available Once you have determined where the EPC 5A subsystem will be physically located in the chas...

Page 18: ...OUT Figure 2 2 Daisy Chain Signal Concept The Slot 1 controller board initiates each daisy chain signal Each VMEbus slot to the right of the Slot 1 controller must pass through each of the daisy chain signals For each VMEbus slot xxxIn pin must be connected to its corresponding xxxOut pin e g BG0In to BG0Out BG1In to BG1Out IackIn to IackOut either through the board in that slot or by jumpers Some...

Page 19: ...jumper needed Figure 2 3 Backplane Jumpers Required for EPC 5A Subsystem The figure above shows the EPC 5A subsystem Note that the left most slot does not require any jumpers All other slots occupied by the subsystem require all five jumpers be installed ...

Page 20: ...MEbus Backplane Jumper Examples Once you have determined where the jumpers need to be you must determine how to jumper your particular backplane Different backplane manufacturers handle this in different ways some provide stake pins on the rear of the backplane while others provide stake pins on the front of the backplane These stake pins can be located in several different places ...

Page 21: ...ot being jumpered as shown in Figure 2 6 above Typically the stake pins are located between the slot being jumpered and the next lower numbered slot e g jumpers for Slot 6 would be located adjacent to Slot 6 between Slots 5 and 6 Consult your VME chassis reference manual or contact the chassis manufacturer if you are unsure where to jumper your particular system BG0 BG1 BG2 BG3 IACK J1 Connector F...

Page 22: ...r to force a BIOS recovery during the boot process BBEN JP1 5 6 FBD boot block write enable Install this jumper to enable writes to the boot block of the FBD FWEN JP1 7 8 FBD write enable except boot block Install this jumper to enable writes to the FBD main blocks 1 3 and 4 and parameter blocks 1 and 2 MODID JP1 9 10 Mod ID routing Remove this jumper for non standard VME backplanes SPEAKER H2 Spe...

Page 23: ...e failure CAUTION The EXP MX mass storage module contains a delicate hard disk Use care during installation Subplane Installation Subplanes are printed circuit boards with connectors on both sides A subplane provides several functions Primarily it acts as the PC AT bus Additionally it provides power from the VMEbus backplane to the EPC 5A and expansion modules How subplanes function is discussed i...

Page 24: ...e connectors on each side After jumpering the backplane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for optional bolting to the VMEbus backplane using the screws included The lower EXM connector is denoted as EXM slot 0 a...

Page 25: ...de and three on the rear After jumpering the backplane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for op tional bolting to the VMEbus backplane using the screws included The EXM slot numbers are shown in the drawing Figu...

Page 26: ...s five connectors on each side After jumpering the backplane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for optional bolting to the VMEbus backplane using the screws included The EXM slot numbers are shown in the drawing...

Page 27: ... the front side and five on the rear After jumpering the back plane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for op tional bolting to the VMEbus backplane using the screws included The EXM slot numbers are shown in the...

Page 28: ... each side After jumpering the backplane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for optional bolting to the VMEbus backplane using the screws included The EXM slot numbers are shown in the drawing Figure 3 5 EXP BP4A...

Page 29: ...The EXP BP6 has eight connectors on the front side and seven on the rear Plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 5A subsystem will occupy The subplane has holes for op tional bolting to the VMEbus backplane using the screws included The EXM slot numbers are shown i...

Page 30: ...d touching the circuit board and connector pins and make sure the environment is static free q Make sure the ejector handles are in the normal non eject position Push the top handle down and the bottom handle up so that the handles are not tilted q Slide the EPC 5A module into the left most slot occupied by the subplane Use firm pressure on the handles to mate the module with the connectors q Tigh...

Page 31: ...ly be used in a VMEbus slot where the subplane has both EXM connectors Simply slide the Module Carrier into place and tighten the two top and bottom retaining screws The following figure shows a side view of an EXP MC containing two EXMs plugged into a subplane that is plugged into a VMEbus backplane EXM Expansion Module EXP MC Module Carrier Subplane VMEbus Backplane EXM Expansion Module Figure 3...

Page 32: ...om front panel screws to hold it firmly in place EXM Module Insertion One or two EXMs may be installed through the front panels of the EPC 5A and each EXP MC Module Carrier To install an EXM q Remove and save the blank face plate from the desired slot q Slide the EXM into place in the card guides Push firmly on the EXM front panel until the EXM card edge connector is firmly seated in the subplane ...

Page 33: ...hose found on IBM compatible desktop PCs and therefore pin by pin details are not given in this chapter Pin outs are specified in Chapter 7 Connectors Monitor Connection of a monitor requires the use of an EXM video controller Consult the video controller manual for details The monitor should be attached and powered on prior to applying power to the EPC 5A If this is not done the EPC 5A cannot det...

Page 34: ...Many current PC AT computers now incorporate 16C550 UARTs The EPC 5A serial ports may be used for connecting a mouse modem serial printer RS 232 link etc Parallel Printer Port The output only parallel port on the front panel is a DB 25 connector that is completely compatible with the corresponding LPT1 connector on IBM PCs and compatibles Typically it is used to connect printers and software secur...

Page 35: ... the screen display and depending on how your system is configured will either pause or attempt to continue BIOS Setup Screens The EPC 5A s BIOS contains a setup function to display and modify the system configuration This information is maintained in the EPC 5A s nonvolatile CMOS RAM and is used by the BIOS to initialize the EPC 5A hardware The BIOS Setup can only be entered during the system res...

Page 36: ...ub menu heading Fields with a triangle to the left are actually sub menu headings press Enter when the cursor rests on one of these headings to reach that sub menu For most fields position the cursor at the field and from the numeric keypad press the and keys to rotate through the available choices Certain numeric fields can also be entered via the keyboard Once the entry has been changed to appea...

Page 37: ...led as the A B drive Possible settings are Not Installed 360 KB 5 720 KB 3 1 2 MB 5 1 44 MB 3 and 2 88 MB 3 The BIOS defaults to Not Installed for drives A and B PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help System Date 03 01 96 IDE Adapter 0 Master C 704 Mb Video System EGA VGA Memory Shadow System Memory 640 KB Extended Memory 31 MB F1 Help Select Item Change Va...

Page 38: ...y Shadow Sub Menu for more information Boot Sequence Sub menu The Boot Sequence Sub menu allows you to change the boot delay the boot sequence and to disable several displays during the boot process such as the SETUP prompt POST errors floppy drive check and summary screen When the boot sequence has been specified in the Boot Sequence sub menu the sequence is displayed in the Boot Sequence field o...

Page 39: ... or Enter selects field Autotype Fixed Disk Press Enter IDE Adapter 0 Master C 704Mb Write Precomp None Sectors Track 63 Heads 16 Cylinders 1365 Type User 704 Mb LBA Mode Control Disabled Figure 4 3 IDE Adapter Sub menu Autotype Fixed Disk Use this option when setting up new disks This option allows the BIOS to determine the proper settings of the disk based on information on the disk which is det...

Page 40: ...isk type is set to Auto but no hard disk is actually present the BIOS will continue to query the non existent hard disk until it times out adding a number of seconds to the duration of the POST Note that there are some restrictions when setting up devices on the EPC 5A If you plan to boot from a non IDE device such as a SCSI hard disk set the C drive type as None and use the BIOS extension LBA Mod...

Page 41: ... in the setup menu is 16KB in size Multiple shadow regions may have to be enabled if the BIOS extension to be shadowed is larger than 16KB System Shadow Video Shadow These options are not editable since the System and VGA BIOS are always shadowed Shadow Memory Regions These options enable or disable shadowing for the associated memory region The default is Disabled PhoenixBIOS Setup Copyright 1985...

Page 42: ...bled SETUP Prompt Enabled Boot Sequence A then C Summary Screen Enabled Figure 4 5 Boot Options Sub menu Boot Delay Use this option to set the system to delay booting for a time period from 0 through 255 seconds This allows for long start up times on boot devices that spin up slowly The default is 0 seconds Boot Sequence This option is used to define how the system treats floppy drive A when booti...

Page 43: ...ounters errors Otherwise the system continues to attempt to boot despite any startup error messages that display Note that this option only affects those errors defined as boot failures See Chapter 9 Troubleshooting and Error Messages for a list of those failures defined as boot failures that are configured to halt the system The default is Enabled Floppy Check This option is used to enable or dis...

Page 44: ...ield NumLock On Keyboard Features Keyboard auto repeat delay 1 4 sec Keyboard auto repeat rate 30 sec Key Click Disabled Figure 4 6 Keyboard Features Sub menu Numlock Use this option to enable or disable the Numlock feature of the keyboard Numlock on enables the use of the keypad numbers The default is Auto Key Click Use this option to enable or disable the key click feature on the keyboard If ena...

Page 45: ...vanced from the Main BIOS Setup menu PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field Warning L1 Cache Enabled Setting items on this menu to incorrect values may cause your system to malfunction Large Disk Access Mode...

Page 46: ...BIOS extensions The screen graphic only shows the first group Two extensions ship with the EPC 5A The PicoFlash BIOS offset is 48000h and the size is 2000h The vRom BIOS offset is 4A000h and the size is 4000h BIOS Extension Offset in FBD This option selects the source address of the BIOS extension located in the FBD The address is an offset from the base of the FBD The offset range is between 4600...

Page 47: ...ot agree with the ID of the card actually installed in the slot an EXM configuration error occurs and the card is not configured For a slot with no EXM card installed enter FFh the default value PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help EXM Slot 0 F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values...

Page 48: ...he second option byte value for the EXM card intended to reside in this slot Option byte 2 is defined by the particular EXM card installed The proper value of this option for a slot with no EXM card installed is not defined The value typically used is 00h the default value C P U 0 1 2 4 3 5 Figure 4 9 Slot Numbering All slots not occupied by an EXM module should show an ID of FF and OB1 OB2 of 00 ...

Page 49: ...ter port is not being used IRQ3 should not be used if the COM B port is being used IRQ4 should not be used if the COM A port is being used 2 Use DMA channels 1 3 6 and 7 3 Do not select I O addresses that conflict with those in the EPC 5A A complete list appears in Appendix A For instance I O addresses in the 300 33F range can be used 4 If the EXM needs to use upper memory addresses they must be i...

Page 50: ...uses when the EPC 5A is the slot 1 controller Selecting Round Robin configures the arbiter to scan the bus request lines from highest priority down to lowest priority and grant the bus to the first requester it finds Selecting Priority configures the arbiter to grant the bus to the highest priority requester at any time The default is Round Robin PhoenixBIOS Setup Copyright 1985 96 Phoenix Technol...

Page 51: ...e Logical Address This option is used to select the ULA for the EPC 5A This logical address is used to uniquely identify and access the EPC 5A in a VXI system The default is ULA F8 VME Boot Scan Range This option is used to select the scan range when booting from VME vROM The ranges are as follows A24SD searches from FF000000h FFF00000h on 100000h boundaries A24SD searches from 00000000h 00F00000h...

Page 52: ... and selective CMOS RAM restore conditions The CMOS RAM configuration backup is stored in FBD parameter block 2 This entire block is reserved for this purpose and cannot be shared The available selections from the Exit setup menu that would force a CMOS restoration are Always restore Never restore and restore on Corrupt CMOS The default setting is to restore on Corrupt CMOS PhoenixBIOS Setup Copyr...

Page 53: ...option is used to save into CMOS the values that have been entered then reboot Discard Changes Exit This option is used to discard the changes just made and revert to the state when Setup was entered The system reboots with the old values Get default values This option is used to reset the Setup values to the original default values that were set at the factory before any suppliers or other end us...

Page 54: ...d BIOS update replacement software from your supplier and have reviewed the documentation and procedures provided with that distribution If you select this option by mistake any changes made to the BIOS are lost unless you have already saved them using the Save Current Values option The system automatically begins searching for the update program that should be on the floppy disk inserted in drive...

Page 55: ... EPC 5A processor board conforms with the VMEbus standard 6U form factor Processor and Coprocessor The processor in the EPC 5A is an Intel486 DX4 running internally at 100 MHz with an external interface at 33 MHz The 486 has a built in math coprocessor and 16K cache Core Logic The system uses the RadiSys R400EX system controller The R400EX was developed by RadiSys to provide flexibility of differe...

Page 56: ...t B Functionality Port B register is located at 061h RadiSys R400EX Core System Support Features DRAM Refresh Controller Supports two banks of SIMMs as Fast Page Mode FPM Extended Data Out EDO or Flash SIMMs Second bank start address is configurable Supports EDO FPM memory type detection SIMM types cannot be mixed Power Management Support This interface is not used on the EPC 5A Programmable Chip ...

Page 57: ...ays used by a video controller as video RAM 0C0000 0C7FFF Write protected DRAM containing video BIOS 0C8000 0DFFFF Uncommitted mapped to EXM interface 0E0000 0EFFFF User mappable hardware window onto VMEbus 0F0000 0FFFFF Write protected DRAM containing BIOS 0C8000 0DFFFF may be used either as page frames i e for Ethernet etc or may be used by DOS as upper memory blocks if an EMM driver is installe...

Page 58: ...vides two NS16C450 compatible serial ports and a parallel port Since LPTOEN ties to low this port is output only The serial ports signal interrupts on IRQ3 and IRQ4 and are accessible at the standard PC AT architecture I O base addresses of 3F8h and 2F8h respectively The parallel port signals interrupts on IRQ7 and is accessible at the standard PC AT architecture I O base address of 378h Real Time...

Page 59: ...do not alter the data Embedded Shadow The EPC 5A supports several different boot methods and operating systems In order to boot from VME or flash it is necessary to first load and execute a BIOS extension The FBD has an unused 96KB region in main block 3 that lies between the end of the PicoFlash extension and start of the System BIOS that can be used for BIOS extension storage In order to use thi...

Page 60: ...e boot device is Flash either VME or SCSI can be selected as the second BIOS recognized device IDE Booting If the boot device is IDE either VME or Flash can be used only after loading the device driver SCSI can be selected as the second BIOS recognized device Battery The battery powers the CMOS RAM and TOD clock when system power is not present At 60 C the battery should have a shelf life of over ...

Page 61: ...cessfully the output is ignored However programs that rely on specific video modes that write directly into the video RAM or that directly call video BIOS functions will fail Front Panel LEDs The EPC 5A has five LEDs in the top left corner of the front panel These LEDs are described below RUN This LED is lit whenever the EPC 5A s CPU is performing bus cycles It first comes on at power up and shoul...

Page 62: ...set another master asserting the reset bit of a register mapped to the VMEbus Asserting this bit causes a hard reset of the system See bit 0 RSTP register 8144h EXM Expansion Interface The EXM expansion interface is electrically similar to the PC AT ISA 16 bit data bus In addition it contains a signal EXMID used for dynamic recognition and configuration of EXMs EXMs respond to one or more I O addr...

Page 63: ...hrough the subplane s 4 row DIN connector B row The only connections to the VME J2 backplane on the B row are power and ground address lines A31 A24 and data lines D16 D31 Pin 30 Row A the VXI defined module identification MODID line is also connected Pin A30 is an input driving one gate input and an 825 ohm pull down resistor It may be disabled by removing the MODID jumper on the EPC 5A If necess...

Page 64: ...required timeout function for data transfer time out it does not provide the optional bus grant timeout If another master has been granted permission to use the data bus but does not access or relinquish the data bus the bus will be hung indefinitely Concepts Memory Map VMEbus accesses are available by mapping a 64K segment of the VMEbus through the 0E0000h 0EFFFFh window or by direct mapping abov...

Page 65: ...th one exception for PC compatibility map onto the VMEbus When direct protected mode addressing of A24 or A16 space the high order nibble is used to define the access mode and byte ordering For A32 space the high order 2 bits define the access mode leaving 30 bits available for addressing Thus only the first 1 Gigabyte of VMEbus A32 space is directly addressable All A24 and A16 space is directly a...

Page 66: ... have to coordinate their use of the VME memory window mapping registers When using the EPC 5A this way to perform VMEbus accesses one would typically set up the VME memory window for interrupt acknowledge accesses Also note that the direct access mappings do not cover the entire VMEbus A32 address range and do not provide all VMEbus defined address modifier encodings but one can use the VME memor...

Page 67: ...an byte ordering When performing a single byte D08 access the byte order makes no difference However word D16 or double word D32 accesses may require byte swapping When little endian is selected bytes pass straight through unchanged Little endian should only be used when reading or writing data between two Intel processor systems The results of using little endian byte ordering to transfer a doubl...

Page 68: ...undary aligned Another consideration is the compiler being used Some compilers produce two 16 bit accesses when a 32 bit access is desired When this occurs again the data will be scrambled When transferring a 32 bit floating point number special care must be taken to assure that both processors use the same floating point format and that both systems expect the mantissa and exponent in the same by...

Page 69: ...erating system As such care must be taken in writing to the EPC 5A s memory When such an access is fielded by the EPC 5A the EPC 5A s A24 or A32 base address is effectively subtracted from the VMEbus address value and the result is treated as if the access came from the 486 However note the following 1 Any access that maps to local addresses 000A0000h 000BFFFFh 000D0000h 000EFFFFh to addresses map...

Page 70: ...o the DRAM the EPC 5A automatically purges the cached entry if it exists Given the above another subtle use for the ability of the EPC 5A to access its own DRAM via a VMEbus access is selective purging of the cache For instance if the EPC 5A is mapped at address base 18000000h in the A32 space and a program is meant to purge location 0000AB00h from the cache a read from 0000AB00h followed by a wri...

Page 71: ...ng that operating system tables e g page tables that are accessed by the CPU by implicit locked accesses are not mapped into VME This would only be a concern for user written operating systems VMEbus Interrupt Response When the EPC 5A s Interrupt Generator register 815F is used to assert an interrupt the EPC 5A formulates a status ID value that is transmitted on the bus as the response to a matchi...

Page 72: ...ess bits 21 16 Res Res 8130h VME A21 16 Address Register 1 1 1 0 1 1 0 0 8140h ID Register lower 1 0 0 A32 1 1 1 1 8141h ID Register upper 1 1 0 0 0 1 0 0 8142h Device Type Register lower 0 Slave Size 1 1 1 1 1 8143h Device Type Register upper SRIE RELM ARBPRI READY PASS NOSF RSTP 8144h Status Control Register lower SLE MODID SYSR SYSF ARBM 1 1 1 8145h Status Control Register upper 1 1 1 1 1 1 1 1...

Page 73: ...High Register upper RAM 814Eh Message Low Register lower RAM 814Fh Message Low Register upper VMEbus Address bits 31 24 WA31 24 8150h Message A31 24 Address Register VME WA23 22 BORD IACK AM5 AM4 AM2 AM1 8151h VME Modifier Register IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8152h VME Interrupt State Register IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8153h VME Interrupt Enable Register 1 1 1 1 1 ACFA BE...

Page 74: ... are cleared by an AT reset that is when the RESET button is pushed or power is applied to the system MEMSIZE Memory Size These bits tell the memory controller how much SIMM DRAM memory is present on the EPC 5A This field is set by the BIOS when power is applied to the EPC 5A and contains one of the following values 001 4 MB 010 8 MB 111 16 MB 110 32 MB Larger memory sizes are not yet defined VME ...

Page 75: ...ts must come from somewhere else Six of them come from this register Bit 7 of this register is used as VME address bit 21 bit 6 as VME address bit 20 and bit 2 as VME address bit 16 The two low order bits are reserved RAM bits On writes assign them the value 0 For compatibility with EPC 1 this register is aliased at I O port addresses 8132h 8134h and 8136h ID Register 8140h 8141h 1 1 1 0 1 1 0 0 L...

Page 76: ... clear the value of the register is 1Fh and the A32 bit in the previous register is 0 This denotes that the EPC 5A responds to a 4 MB range in the A24 space The remaining ROM bits define the EPC 5A as having a model code of 4036 Status Control Register 8144h 8145h SRIE RELM ARBPRI READY PASS NOSF RSTP Lower SLE MODID SYSR SYSF ARBM 1 1 1 Upper This register adheres to the VXIbus specification and ...

Page 77: ...he EPC 5A SLE Slave enable If set the EPC 5A responds to certain A24 or A32 accesses on the VMEbus MODID This readable bit is connected to pin 30 in row A of the VMEbus P2 con nector If clear 0 it denotes that the pin is being pulled high This is used in VXI systems for module identification SYSR SYSRESET The EPC 5A asserts the VME SYSRESET line while this bit is 1 When using this bit it is the so...

Page 78: ...handshake mode Response Register 814Ah 814Bh LOCK 1 ABMH 1 1 ULA Lower 0 0 0 0 1 RRDY WRDY 1 Upper With the exception of LOCK this register is defined by the VXIbus specification It contains control bits associated with the message registers LOCK If set the message register can be locked for the sending of a message If clear the message register has been locked ABMH This bit is cleared when the me...

Page 79: ... message low register For a 32 bit message the sender writes first into the message high register and then the message low register Message High Register 814Ch 814Dh RAM Lower RAM Upper This register is an extension of the following register for 32 bit messages An access to this register clears flag ABMH in the response register Message Low Register 814Eh 814Fh RAM Lower RAM Upper This register is...

Page 80: ... does not support user defined address modifiers BORD Byte order This bit controls the ordering of data bytes for D16 and D32 VMEbus accesses If 0 the bytes are transmitted in little endian Intel order if 1 byte swapping hardware transmits the bytes in big endian Motorola order Refer to the previous section in this chapter on byte ordering IACK This bit when set is used to define the VMEbus access...

Page 81: ...Q10 interrupt If the bit is 0 the condition is present ACFA VMEbus ACFAIL is asserted BERR An access from the EPC 5A to the VMEbus was terminated with a BERR bus error SYSF VMEbus SYSFAIL is asserted All bits are read only except BERR BERR is a sticky bit that is cleared whenever an access from the EPC 5A is terminated by a bus error and remains clear 0 unless changed by software by writing any va...

Page 82: ...S1 data strobe signal is as serted It may be used for bus monitoring res This bit should always be set 1 The EPC 3 contains two additional bits in this register ENMI and DEAD for breaking deadlock situations on its dual port DRAM These situations cannot exist in the EPC 5A so the signals are not implemented VME Interrupt Generator Register 815Fh 1 1 1 1 1 INTERRUPT OUT This register is used to ass...

Page 83: ...rs are de fined below Offset from ULA Upper byte Lower byte 0 ID 8141h ID 8140h 2 Device type 8143h Device type 8142h 4 Status control 8145h Status control 8144h 6 Slave offset 8147h Slave offset 8146h 8 Protocol 8149h Protocol 8148h A Response 814Bh Response 814Ah C Message high 814Dh Message high 814Ch E Message low 814Fh Message low 814Eh The registers occupy the first 16 bytes of the 64 byte s...

Page 84: ...l bits however are cleared by a power on reset However this may not be apparent because the BIOS initialization sequence then reinitializes values in these register fields largely as a result of the non volatile configuration information specified in the setup screen The BIOS clears the interrupt enable and event enable registers Supported Address Modifiers 2Dh A16 supervisor 39h A24 non privilege...

Page 85: ...cess 2Dh 3 The unused address lines A31 A16 may float when not being used Registers 8150h and 8130h must be set so that each line is a 1 Set register 8130h to FCh and register 8150h to FFh 4 Set the access mode in the VME Modifier Register 8151h as follows VME WA23 22 BORD IACK AM5 AM4 AM2 AM1 Note that register bits are not defined for the VMEbus address modifier lines AM3 and AM0 since for all d...

Page 86: ...d be set to 1100 1010 or CAh 5 Map the address Add the A16 address to the memory window address Addr E0000000h A16 address 6 Read the data Data value pointed to by Addr Microsoft C code for Example 1 define WORD unsigned short define LWORD unsigned long WORD addr 16 bit A16 address WORD data WORD far wptr outp 0x8104 inp 0x8104 2 set VME access bit outp 0x8130 0xFC outp 0x8150 0xFF outp 0x8151 0xC...

Page 87: ... 3 Determine the correct address modifier for A32 supervisory access 4 Calculate the value and set register 8151h as follows VME WA23 22 BORD IACK AM5 AM4 AM2 AM1 Bits 7 6 VME address bits 23 22 Bit 5 BORD 0 Bit 4 IACK 0 Bits 3 0 Bit 3 Address Modifier bit 5 Bit 2 Address Modifier bit 4 Bit 1 Address Modifier bit 2 Bit 0 Address Modifier bit 1 5 Set register 8130h with the value corresponding to b...

Page 88: ...irst wait until the DONE bit is set Low Level Handling of VMEbus Interrupts The following is a description of how VMEbus interrupts IRQ1 IRQ7 VXIbus message interrupts and error interrupts BERR ACFAIL WDTG etc should be handled on the EPC 5A Note that in general the use of EPConnect is highly recommended to handling interrupts Enable the appropriate registers VME Interrupt enable 8153h and VME Eve...

Page 89: ...controllers by sending both interrupt controllers an End of Interrupt EOI You must make sure that your interrupt handler code is not re entered while dispatching interrupts Either all interrupts should be disabled or IRQ10 should be masked after doing the EOI to the interrupt controller Remember to re enable them prior to leaving the interrupt handler If you are using DOS you may need to switch to...

Page 90: ... 2 Establish a byte ordering for the status ID to be read Whether this is an 8 bit or 16 bit read is dependent on the card issuing the interrupt 3 The address modifiers and transfer length are dependent on the hardware generating the interrupt 4 Perform a read of the VMEbus where the address being read reflects the interrupt level being responded to Address lines A3 A1 must reflect the interrupt l...

Page 91: ...her active interrupts This includes all other interrupts and errors which come in prior to calling the interrupt handling routine as well as any new interrupts and errors which may occur during this process Only when all interrupts and error conditions are handled may you return from the overall interrupt handler Again if you miss any interrupts or errors no other interrupts or errors are recogniz...

Page 92: ...EPC 5A Hardware Software Reference Manual Page 86 6 6 NOTES ...

Page 93: ...bed in the separate manuals for those products All but the battery and speaker headers are on the front panel Pins are labeled from the point of view of looking into the front of the connector on the EPC 5A Serial Ports The COM1 and COM2 serial ports are DB 9 DTE connectors defined in the following table Pin Signal Pin Signal 1 Carrier detect 6 Data set ready 2 Receive data 7 Request to send 3 Tra...

Page 94: ... 17 Select in 5 DB3 18 Signal ground 6 DB4 19 Signal ground 7 DB5 20 Signal ground 8 DB6 21 Signal ground 9 DB7 22 Signal ground 10 Acknowledge 23 Signal ground 11 Busy 24 Signal ground 12 Paper end 25 Signal ground 13 Select Table 7 2 Parallel Port Pinout Keyboard The keyboard connector is a 6 pin DIN defined as Pin Signal Pin Signal 1 Data 4 5V 2 not used 5 Clock 3 Ground 6 not used Table 7 3 Ke...

Page 95: ...rcuit board and is defined as Pin Signal Pin Signal 1 Reference voltage 2 Speaker tone Table 7 4 Speaker Header Pinout Battery Header The battery header is located on the EPC 5A circuit board and is defined as Pin Signal Pin Signal 1 VBATT 3 Ground 2 key 4 Ground Table 7 5 Battery Header Pinout 1 2 ...

Page 96: ...EPC 5A Hardware Software Reference Manual Page 90 2 2 7 7 NOTES ...

Page 97: ...Ms with the following specifications 72 pin fast page mode 60 nanosec or better single sided For 8 MB Use 2 each 1M x 36 SIMMs RadiSys P N 70 0074 For 16 MB Use 1 each 4M x 36 SIMMs RadiSys P N 70 0075 For 32 MB Use 2 each 4M x 36 SIMMs RadiSys P N 70 0075 For 64 MB Use 2 each 8M x 36 SIMMs RadiSys P N 70 0150 The SIMMs used in the EPC 5A are publicly available Contact RadiSys Technical Support fo...

Page 98: ...SIMM Memory Location After upgrading the memory power up the machine and press F2 to enter the Main BIOS Setup Menu Verify that the top line of this screen shows the correct amount of memory Save and reboot The system reboots and no error messages should be displayed ...

Page 99: ... to boot evidenced by RUN LED being on floppy and hard disk being accessed but provides no video Video adapter not fully seated in subplane Monitor or cable problem Video adapter failure Subplane failure EPC 5A cannot talk to EXM expansion interface Remove the video adapter If the subplane is secured to the VMEbus backplane by retaining screws check for over tightening of the screws Reinsert the v...

Page 100: ...ne 12V and 12V are good An EXM module is using the same interrupts as COM1 and or COM2 Verify that no other card in the EPC 5A subsystem is using IRQ3 or IRQ4 Call RadiSys Technical Support System will not talk across VMEbus The VMEbus backplane may not be jumpered correctly More than 1 master may be set to provide Slot 1 functions EPC 5A or subplane may have bent pins VMEbus interface failure See...

Page 101: ...at the specified or default directory level of the boot disk or the SHELL statement in your CONFIG SYS lists the file incorrectly wrong directory or misspelled CMOS CHECKSUM INVALID Problem Something in the nonvolatile CMOS RAM is incorrect Solution s Run the BIOS setup program to determine what is wrong and correct it If the error occurs repeatedly the EPC 5A s battery has failed CMOS RAM ERROR C...

Page 102: ...ISKETTE DRIVES OR TYPES MISMATCH ERROR RUN SETUP Problem The floppy diskette s installed in the system do not match the configuration information listed in the BIOS setup screen This may be due to incorrect entries in the BIOS setup screen or one or both drives may not be responding at power up Solution s Run the BIOS setup program Make sure the BIOS setup entries relating to floppy drives correct...

Page 103: ...the device being used EXM CONFIGURATION ERROR Problem The EXMs installed or not installed do not match the configuration information in the CMOS Setup Solution s Run the BIOS setup program Enter the EXM menu Verify the information listed on the screen save any changes and reboot If necessary refer to the section EXM Setup Screen and or your EXM manual s for more details FLOPPY DISK CNTRLR ERROR OR...

Page 104: ...al partition KEYBOARD ERROR OR NO KEYBOARD PRESENT Problem This message indicates that the system did not recognize a keyboard at power up or you pressed a key during the power on self test Solution s Check the integrity of the keyboard connector If you think you pressed a key during power up reboot the system using the front panel reset button Some keyboards are designed with a switch or jumper t...

Page 105: ...d Disk Menu Select the correct drive type to match the type used to format the disk originally Save the changes and reboot the system This can also occur if the hard disk is partitioned and one partition is set active but the partition was not formatted NON SYSTEM DISK OR DISK ERROR REPLACE AND PRESS ANY KEY WHEN READY Problem This is caused by an attempt to boot from a disk or diskette that is no...

Page 106: ...memory location specified in your software is valid PRESS A KEY TO REBOOT Problem A C drive partition exists but is not set active Solution s Run your operating system disk partitioning program like FDISK and set the primary partition active REAL TIME CLOCK ERROR RUN SETUP Problem The battery backed TOD clock is incorrect Solution s Run the BIOS setup program to determine what is wrong and correct...

Page 107: ...Chapter 9 Troubleshooting Error Messages Page 101 9 9 ...

Page 108: ...ed out Drive initialization failed Drive recalibration failed Last track seek failed 2 Timer error Causes System timer 0 failed 3 I O chip error Causes I O conflicts exist for serial and parallel ports hard disk any or all 4 Other error Causes IRQ conflicts The System BIOS prints an error message but does not halt when it encounters the following error conditions 1 RTC error Causes RTC lost power ...

Page 109: ...Bh Enable CPU cache 0Ch Initialize cache to initial POST values 0Eh Initialize I O 0Fh Initialize localbus IDE 11h Load alternate registers with initial POST values 12h Jump to UserPatch0 14h Initialize keyboard controller 1 2 2 3 16h BIOS ROM checksum 18h 8254 timer initialization 1Ah 8237 DMA controller initialization 1Ch Reset programmable interrupt controller 1 3 1 1 20h Test DRAM refresh 1 3 ...

Page 110: ... 4Eh Display copyright notice 50h Display CPU type and speed 51h Initialize EISA board 52h Test keyboard 54h Set key click if enabled 56h Enable keyboard 2 2 3 1 58h Test for unexpected interrupts 5Ah Display prompt Press F2 to enter SETUP 5Ch Test RAM between 512KB and 640KB 60h Test extended memory 62h Test extended memory address lines 64h Jump to UserPatch1 66h Configure advanced cache registe...

Page 111: ...ss line 95h Install CDROM for boot 96h Clear huge ES segment register 1 2 98h Search for option ROMs beep for bad checksum 9Ah Shadow option ROMs 9Ch Set up power management 9Eh Enable hardware interrupts A0h Set time of day A2h Check keylock A4h Initialize typematic rate A8h Erase F2 prompt AAh Scan for F2 keystroke ACh Enter SETUP AEh Clear in POST flag B0h Check for errors B2h POST done prepare...

Page 112: ... NuBIOS Auxiliary Checkpoint Codes Beep Code Post Code Checkpoint Description E2h Initialize the system controller E3h Initialize refresh counter E4h Check for forced flash E5h Check HW status of ROM E6h BIOS ROM is OK E7h Do a complete RAM test E8h Do OEM initialization E9h Initialize interrupt controller EAh Read in bootstrap code EBh Initialize all vectors ECh Boot the flash program EDh Initial...

Page 113: ...spond by E mail phone or FAX by the next business day Technical Support Services are designed for customers who have purchased their products from RadiSys or a sales representative If your RadiSys product is part of a piece of OEM equipment or was integrated by someone else as part of a system support will be better provided by the OEM or system vendor that did the integration and understands the ...

Page 114: ...ave indicated that issues of serial number tracking and version control make it more convenient to receive their original products back after repair Warranty Repairs Products under warranty see warranty information in the front of this manual will have manufacturing defects repaired at no charge Products sent in for warranty repair that have no faults will be subject to a recertification charge Ex...

Page 115: ...ers want or need the option of repairing their own equipment all components are available in a spares program There is a minimum billing charge associated with this program Arranging Service To schedule service for a product please call RadiSys RMA Dispatcher directly at 800 256 5917 Have the product model and serial numbers available along with a description of the problem An RMA Dispatcher will ...

Page 116: ... address contact names and phone numbers in purchasing and engineering and a description of the suspected problem Any ancillary information that might be helpful with the debugging process will be appreciated Other Countries Contact the sales organization from which you purchased your RadiSys product for service and support ...

Page 117: ...nnel 2 address 005 Channel 2 count 006 Channel 3 address 007 Channel 3 count 008 Command status 009 DMA request 00A Command register R Single bit DMA req mask W 00B Mode 00C Set byte pointer R Clear byte pointer W 00D Temporary register R Master clear W 00E Clear mode reg counter R Clear all DMA req mask W 00F All DMA request mask First Interrupt controller R400 emulating 8259 of PC AT I O Addr Fu...

Page 118: ...k R400 emulating MC6818 of PC AT I O Addr Functional group Usage 070 Real time clock RTC index reg NMI enable 071 RTC data register 0 seconds 1 seconds alarm 2 minutes 3 minutes alarm 4 hours 5 hours alarm 6 day of week 7 date of month 8 month 9 year A status A B status B C status C D status D E RAM 3F RAM DMA Page Registers R400 emulating 74LS612 of PC AT I O Addr Functional group Usage 081 DMA C...

Page 119: ...ctional group Usage 0C0 DMA Channel 4 address 0C2 Channel 4 count 0C4 Channel 5 address 0C6 Channel 5 count 0C8 Channel 6 address 0CA Channel 6 count 0CC Channel 7 address 0CE Channel 7 count 0D0 Command status 0D2 DMA request 0D4 Command register R Single bit DMA req mask W 0D6 Mode 0D8 Set byte pointer R Clear byte pointer W 0DA Temporary register R Master clear W 0DC Clear mode reg counter R Cl...

Page 120: ...Interrupt ID register 2FB Line control register 2FC Modem control register 2FD Line status register 2FE Modem status register Parallel I O LPT1 Port TI 16C452 emulates PC AT chipset I O Addr Functional group Usage 378 LPT1 parallel port Printer data register 379 Printer status register 37A Printer control register Serial I O ComA Port TI 16C452 emulates PC AT chipset I O Addr Functional group Usag...

Page 121: ...atus control low 8145 Status control high 8146 Slave offset low 8147 Slave offset high 8148 Protocol low 8149 Protocol high 814A Response low 814B Response high 814C Message high low 814D Message high high 814E Message low low 814F Message low high 8150 VME map WA31 24 8151 VME modifier 8152 VME interrupt state 8153 VME interrupt enable 8154 VME event state 8155 VME event enable 8156 Module status...

Page 122: ...EPC 5A Hardware Software Reference Manual A A Page A 6 NOTES ...

Page 123: ...el check IRQ0 timer IRQ1 keyboard IRQ2 IRQ8 IRQ15 cascade through IRQ2 IRQ3 COM B serial port IRQ4 COM A serial port IRQ5 unassigned IRQ6 usually needed for floppy disk controller IRQ7 LPT1 parallel port IRQ8 clock IRQ9 unassigned IRQ10 VME interrupt event IRQ11 unassigned IRQ12 unassigned IRQ13 coprocessor IRQ14 used by optional IDE disk controller IRQ15 unassigned Table B 1 EPC 5A Interrupts ...

Page 124: ...hown in the following table 0 unassigned 8 bit 1 unassigned 8 bit 2 usually needed for floppy disk 8 bit 3 usually needed for SCSI disk 8 bit 4 Channel 0 Channel 3 cascade through Channel 4 5 unassigned 16 bit 6 unassigned 16 bit 7 unassigned not connected to EXM expansion interface 16 bit Table B 2 EPC 5A DMA Channels ...

Page 125: ... is protected against accidental writes by a jumper This jumper JP1 5 6 BB_ENB is provided on the board should a code change to the boot block become necessary Main blocks 1 3 4 and both parameter blocks are protected against accidental writes by a write enable bit in the R400EX accessible by the System BIOS Jumper JP1 7 8 also protects the FBD An INT15 Flash Control API interface can be used to c...

Page 126: ...oFlash BIOS 16KB vROM BIOS 8KB Manufacturing BIOS 8KB 8KB Parameter Block 1 System BIOS FFFFC000h FC000h FFFFBFFFh FBFFFh FFFFA000h FA000h FFFF9FFFh F9FFFh FFFF8000h F8000h FFFF7FFFh F7FFFh FFFE0000h E0000h FFFDFFFFh N A FFFC0000h N A FFF80000h N A FFF9FFFFh N A FFFA0000h N A FFFBFFFFh N A 128KB Main Block 2 CSR Data 128KB Main Block 1 Application Storage Device Offset 00000h 40000h 3FFFFh 20000h ...

Page 127: ...alled in the system References in this section to MS DOS refer to MS DOS 6 22 or the Windows 95 command line interface available during the boot process before the Graphical User Interface GUI is started There is no native reflashing support for other protected mode operating systems such as Windows NT OS 2 QNX etc Reflashing on these operating systems must be accomplished by using the recovery pr...

Page 128: ... that the recovery is in progress by a series of beeps The first set of beeps denotes the reading of the BIOS image file while the last set of beeps denotes the erasing and programming of the FBD A final long beep denotes that the system is about to reset after having successfully recovered the FBD The force recovery jumper JP1 FRCUPDT must be removed after the recovery process begins and before t...

Page 129: ...he update process is outlined in the following flow chart Figure C 2 Flash Boot Device Recovery Mechanism Force jumper installed yes no start no yes Checksum OK no yes Load Do floppy recovery Reboot CMOS Reflash byte on Turn off CMOS Reflash b t ...

Page 130: ...r method also copies the special boot sector required by the recovery process If the boot sector is not copied correctly or is somehow corrupted the recovery process does not function correctly The boot sector is not required however for updates Reflashing using REFLASH EXE The FBD can also be reprogrammed using the RadiSys MS DOS utility REFLASH EXE This is a flash read modify write utility that ...

Page 131: ... byte of the flash device C Erase CSR data if it exists and invalidate CMOS data parameter data This option is recommended for BIOS reflashes If the System CMOS data map changes the CMOS data and its map will be inconsistent S Suppress rebooting after successful execution This option is useful for execution from batch files P Physical base address of the region to be flashed This parameter does no...

Page 132: ... order to use this area for BIOS extensions it is necessary to first program the image into the FBD using REFLASH EXE and then at run time copy the BIOS extension from the FBD into DRAM and have the System BIOS scan that region for BIOS extensions Multiple BIOS extensions can be programmed into the user block of the FBD Setup items in the Advanced menu allows the user to select up to 3 BIOS extens...

Page 133: ... FBD in the Advanced menu selects a starting address of one of these blocks The Setup field named BIOS Extension Size in the Advanced menu selects the ending address when added to the BIOS Extension Offset in FBD BIOS Extension Offset in FBD 40000h BIOS Extension Size 2000h The image contained in this block is shadowed into DRAM at the address selected in by the Destination Address Setup field MFG...

Page 134: ...EPC 5A Hardware Software Reference Manual Page C 10 C C NOTES ...

Page 135: ...driver PFORMAT EXE The format utility PFA2 BIN The BIOS extension REFLASH EXE Utility to flash the BIOS extension Step 1 Load the driver This can be done either as a BIOS extension or as a device driver Step 1A Load as device driver Add the line DEVICE PFA2 SYS to your CONFIG SYS file The jumpers on the board for linear paged mode and byte word access to the RFA should be set to byte mode and page...

Page 136: ...emory from 0x4C000 0x4FFFF Inform the setup menu of how to load the extension Now reboot the machine and go into setup by hitting the F2 key at boot time and enter the Embedded Features menu In this menu one of the three Embedded Shadow Regions specify the Offset of BIOS extension in FBD as 0x4C000 and the BIOS extension size as 04000 Next the Destination Address needs to be specified Depending on...

Page 137: ... on the drive When the format completes give the drive a volume label This should complete the process of making the RFA into a Flash File System If you are going to use the RFA as a bootable device the system must be transferred to the RFA device This can be done by using the DOS SYS command The RFA should now be set up for use as a DOS Flash File System The standard DOS copy delete and other uti...

Page 138: ...EPC 5A Hardware Software Reference Manual Page D 4 D D NOTES ...

Page 139: ...er although octal hexadecimal and decimal numbers are often used for convenience Advanced Power Management APM 1 1 A software interface specification that allows operating system device drivers to control the power management functionality of a PC American National Standards Institute ANSI An organization dedicated to advancement of national standards related to product manufacturing AT Bus Attach...

Page 140: ...in binary file format consisting of initialization data setup configuration data diagnostic sequences and other instructions necessary to start up a computer and prepare it to load an operating system BIOS Recovery A process whereby an existing corrupt BIOS image in the flash boot device is overwritten with a new image Also referred to as a flash recovery BIOS Update A process whereby an existing ...

Page 141: ...rom the DRAM controller to an internal DRAM latch register specifying the column at which to read or write data The DRAM requires a column address and a row address to define a memory address Since both parts of the address are applied at the same DRAM inputs use of column addresses and row addresses in a multiplexed array allows use of half as many pins to define an address location in a DRAM dev...

Page 142: ... with a hardware device The software interface to the driver is standardized such that application software calling the driver requires no specific operational information about the hardware device Dual In Line Package DIP A semiconductor package configuration consisting of a rectangular plastic case with two rows of pins one row on each lengthwise side Dynamic Random Access Memory DRAM Semiconduc...

Page 143: ...orage medium Fixed disk storage devices use inflexible disk media and are sealed to prevent data loss due to media surface contamination Fixed disks generally provide the most storage space for a given cost when compared to semiconductor tape and other popular mass storage technologies Field Programmable Gate Array FPGA A large general purpose logic device that is programmed at power up to perform...

Page 144: ...5 Host Bus The address data bus that connects the CPU and the chipset I Industry Standard Architecture ISA A popular microcomputer expansion bus architecture standard The ISA standard originated with the IBM PC when the system bus was expanded to accept peripheral cards Input Output I O The communication interface between system components and between the system and connected peripherals Integrate...

Page 145: ... A set of male connector pins on a circuit board over which can be placed coupling devices to electrically connect pairs of the pins By electrically connecting different pins a circuit board can be configured to function in predictable ways to suit different applications K Kilobyte KB or KByte Approximately one thousand bytes 210 1024 bytes exactly L Logical Address The memory mapped location of a...

Page 146: ...er design first introduced by IBM in the early 1980s Personal System 2 PS 2 Computers designed with IBM s proprietary bus architecture known as Micro Channel Phase Locked Loop PLL A semiconductor device which functions as an electronic feedback control system to maintain a closely regulated output frequency from an unregulated input frequency The typical PLL consists of an internal phase comparato...

Page 147: ...roduce a desired sum of products output function R Random Access Memory RAM Memory in which the actual physical location of a memory word has no effect on how long it takes to read from or write to that location In other words the access time is the same for any address in memory Most semiconductor memories are RAM Read Only Memory ROM A broad class of semiconductor memories designed for applicati...

Page 148: ...alt to internal processing and resets most CPU registers to 0 The CPU then jumps to a starting address vector to begin the boot process Resident Flash Array RFA The RFA represents flash memory that is resident on the hardware platform that is utilized for OS or application purposes RS 232 A popular asynchronous bi directional serial communication protocol Among other things the RS 232 standard def...

Page 149: ...Inline Memory Module SO DIMM A new form factor for memory modules that is smaller and denser than SIMMs Standoff A mechanical device typically constructed of an electrically non conductive material used to fasten a circuit board to the bottom top or side of a protective enclosure Static Random Access Memory SRAM A semiconductor RAM device in which the data will remain permanently stored as long as...

Page 150: ...s information the BIOS uses it to automatically set up the drive for use with the system V Video Electronics Standards Association VESA A group of hardware and software vendors that define specifications for hardware and software interfaces for a variety of devices Video Graphics Adapter VGA A popular PC graphics controller and display adapter standard developed by IBM The standard specifies among...

Page 151: ...95 100 BERR 58 63 75 82 BG0 BG3 10 BG0In BG3In 10 BG0Out BG3Out 10 big endian 59 61 64 BIOS 3 24 25 68 78 96 G 2 BIOS Data Area G 2 BIOS extension term defined G 2 BIOS Recovery term defined G 2 BIOS setup 54 BIOS Update term defined G 2 block transfers 63 Boot Block term defined G 2 Boot device term defined G 2 Boot Sequence term defined G 3 BP2 16 BP3A 18 BP4 17 BP4A 20 BP5 19 BP6 21 bus arbiter...

Page 152: ...DRAM options 48 Driver term defined G 4 DTACK 63 dual ported memory 3 63 Dynamic Random Access Memory DRAM term defined G 4 E EDO DRAMs term defined G 5 electrical specs 4 electrostatic discharge 7 EMM driver 49 Environmentals 4 EPC 1 compatibility 69 EPC 3 compatibility 76 EPConnect 57 62 79 82 EPROM 51 error messages 95 ESD 7 ESD damage 15 Ethernet 3 EXM 3 8 10 15 16 18 19 23 24 25 53 54 EXM CON...

Page 153: ...signments 41 interrupt acknowledge 60 74 76 interrupt acknowledge cycle 65 interrupt acknowledge signal 10 interrupt generator register 65 interrupt mapping B 1 Interrupt Request IRQ term defined G 7 interrupts 83 IRQ10 interrupt 75 J J1 connector 12 57 J2 connector 57 jumper 7 8 10 57 jumpers 11 12 term defined G 7 K keyboard 25 keyboard adapter 25 keyboard connector 88 keyboard errors 98 L LEDs ...

Page 154: ...ERROR 100 PC add in card 3 PC AT bus 15 PCMCIA 3 peripherals 3 8 25 Physical Address term defined G 8 power 15 Power On Self Test POST term defined G 9 power on self test 54 printer port 26 41 priority 57 priority arbiter 71 Priority levels 30 processor 47 protected mode 59 R Random Access Memory RAM term defined G 9 Read ready 72 Real Mode Address tem defined G 9 REAL TIME CLOCK ERROR 100 reboot ...

Page 155: ...fined G 11 T technical support 107 world wide web access 107 Test 53 Test LED 71 TI83000 47 Timer Counter 3 TOD clock 52 100 troubleshooting 93 U unique logical address 65 72 77 upgrades 91 User Editable Drive UED term defined G 12 V VGA term defined G 12 video 3 25 51 video adapter 25 video BIOS 49 video controller 25 53 video RAM 53 VME access bit 68 VME address bits 69 VME backplane 15 VME chas...

Page 156: ...EPC 5A Hardware Software Reference Manual Page I VI NOTES ...

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