RadiSys EPC-5A, Hardware & Software Reference Manual

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EPC-5A Hardware & Software Reference Manual
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Microsoft C code for Example 2 -
LWORD addr; /* 32-bit A32 address */
BYTE data;
BYTE far * wptr;
outp(0x8104,(inp(0x8104)|2)); /* set VME access bit */
outp(0x8150,(WORD)(addr >> 24)); /* A31-A24 */
outp(0x8151,2 | (((addr << 8) >> 30) << 6));
/* A23-A22 and address modifier for A32 supervisory data access */
outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A16 */
wptr = (BYTE far *) (0xE00 (addr & 0X0000FFFFL));
*wptr = data; /* Write through window */
The success of the access can be checked either by enabling BERR as an interrupt or
by looking at the BERR bit in the event state register (8154h) after each access. Since
writes are pipelined, software that looks at the BERR bit should first wait until the
DONE bit is set.
Low-Level Handling of VMEbus Interrupts
The following is a description of how VMEbus interrupts (IRQ1-IRQ7), VXIbus
message interrupts and error interrupts (BERR, ACFAIL, WDTG, etc.) should be
handled on the EPC-5A. Note that, in general, the use of EPConnect is highly
recommended to handling interrupts.
•
Enable the appropriate registers (VME Interrupt enable (8153h) and VME Event
enable (8155h) registers) to allow the interrupts you want to respond to.
•
Enable IRQ10 on the EPC’s equivalent of the 8259h interrupt controller.
•
A VXIbus message interrupt is generated when a master (this EPC-5A or another
master) writes to the Message Low register (16-bit) or the Message High and
Message Low registers (32-bit) from the VMEbus. A message interrupt does not
occur when the EPC-5A writes to its own message register(s) from the PC I/O
space.