RadiSys EPC-5A, Hardware & Software Reference Manual

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EPC-5A Hardware & Software Reference Manual
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Self Accesses Across the VMEbus
Since the EPC-5A’s DRAM can be mapped into the VMEbus A24 or A32 address
space, the EPC-5A can access its DRAM in an alternate way - by generating VMEbus
accesses to addresses mapped as the EPC-5A’s VME slave memory. This can be of
use in multiple-processor systems where some of the EPC-5A’s DRAM is used as
shared global memory; it means that the EPC-5A can access the global memory with
the same addresses as used by other processors without needing to understand that the
memory is actually on-board.
This ability is also useful in system checkout (i.e., checking operation of the
backplane) and in giving an EPC-5A program the ability to view its memory in big
endian format.
A24 and A32 slave accesses result in accesses to the on-board DRAM and never to
the cache. Because the EPC-5A’s cache is a write-through cache, there is never a
discrepancy between data in the cache and the DRAM. When a slave access results in
a write into the DRAM, the EPC-5A automatically purges the cached entry, if it exists.
Given the above, another subtle use for the ability of the EPC-5A to access its own
DRAM via a VMEbus access is selective purging of the cache. For instance, if the
EPC-5A is mapped at address base 18000000h in the A32 space and a program is
meant to purge location 0000AB00h from the cache, a read from 0000AB00h
followed by a write of the read data back to 1800AB00h will accomplish the task.
Read-Modify-Write Operations
VMEbus RMW (read-modify-write) cycles can be performed through use of the
LOCK instruction prefix with certain instructions. All of these instructions perform a
read followed by a write. When such a read occurs that is mapped to the VMEbus,
the EPC-5A treats it as the start of a VME RMW cycle. The next VME access from
the CPU is treated as the write that terminates the RMW cycle. Keep in mind that
accesses that cross a 32-bit boundary are actually performed as two accesses. For this
reason, RMW accesses that cross a 32-bit boundary will not behave as expected.
The EPC-5A provides synchronization integrity in its local DRAM between accesses
from the CPU into the DRAM and RMW VME accesses from other masters into the
DRAM.