RadiSys EPC-5A, Hardware & Software Reference Manual

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Chapter 6: The VMEbus Interface
Page 65
When a VMEbus slave read access occurs to the local DRAM, the EPC-5A watches
the VMEbus data and address strobes to determine if the cycle is an RMW cycle. If it
is, accesses by the CPU are held up until the terminating access of the RMW cycle
occurs.
When the CPU performs a locked access (e.g., via an instruction using the LOCK
instruction prefix) to the local DRAM or the cache, VMEbus slave accesses are held
up until the last locked access completes.
One more case of interest is when the EPC-5A performs a locked access that results in
a self access. These function correctly (i.e., as if the access was not a self access),
providing that operating-system tables (e.g., page tables) that are accessed by the CPU
by implicit locked accesses are not mapped into VME. This would only be a concern
for user-written operating systems.
VMEbus Interrupt Response
When the EPC-5A’s Interrupt Generator register (815F) is used to assert an interrupt,
the EPC-5A formulates a status/ID value that is transmitted on the bus as the response
to a matching interrupt acknowledgment cycle. The EPC-5A acts as both a D08(O)
and D16 interrupter. For D08 interrupt acknowledge cycles, the status/ID value is the
EPC-5A’s logical address (11111aaa, where aaa is the value of ULA as defined in port
814A). For D16 and D32 interrupt acknowledge cycles, the status/ID value consists
of 16 bits. The upper eight bits are the upper half of the response register (the value in
I/O port 814B) and the lower eight bits are the logical address.