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1261B User Manual
Using The Enhanced Monitoring System 4-16
Racal Instruments
Ó
1995
Table 4-6, Time Condition and Event Register Bit Assignments
Bit
Set When
0
Present Power-On Time exceeds limit
1
Cumulative Power-On Time exceeds limit
2
Filter Service Time exceeds limit
Table 4-7, VXI Condition and Event Register Bit Assignments
Bit
Set When
0
VXI Bus Error (BERR*) Count exceeds limit
1
VXI SYSFAIL* is asserted
2
VXI ACFAIL* is asserted
3
VXI IACK1 Count exceeds limit
4
VXI IACK2 Count exceeds limit
5
VXI IACK3 Count exceeds limit
6
VXI IACK4 Count exceeds limit
7
VXI IACK5 Count exceeds limit
8
VXI IACK6 Count exceeds limit
9
VXI IACK7 Count exceeds limit
The “Event Register” holds the latched status of each of the
individual items monitored. Each “Event Register” has the same
bit assignment as the corresponding “Condition Register”.
Thus, the “Voltage Event Register” has the same bit assignment
as that shown in
Figure 4-1.
The difference between the “Condition Register” and the “Event
Register” is that the “Event Register” holds
latched
status
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