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1261B User Manual
Using The Enhanced Monitoring System 4-12
Racal Instruments
Ó
1995
SENSE:VXI:IACK2:COUNT?
-- read IACK2 count
SENSE:VXI:IACK3:COUNT?
-- read IACK3 count
SENSE:VXI:IACK4:COUNT?
-- read IACK4 count
SENSE:VXI:IACK5:COUNT?
-- read IACK5 count
SENSE:VXI:IACK6:COUNT?
-- read IACK6 count
SENSE:VXI:IACK7:COUNT?
-- read IACK7 count
Clearing The VXI
Bus Error and
IACKn Counters
The present count of Bus Error (BERR) or Interrupt
Acknowledge cycles (IACKn) may be cleared to zero. This is
necessary since the count increases to a maximum value of 256.
Once the count reaches 256, the only way to clear it is to use the
command described below (or to select some other IACKn or
BERR line for monitoring).
The following commands may be used to clear the BERR or
IACKn counters:
SENSE:VXI:BERR:CLEAR
-- clear BERR counter
SENSE:VXI:IACK1:CLEAR
-- clear IACK1 counter
SENSE:VXI:IACK2:CLEAR
-- clear IACK2 counter
SENSE:VXI:IACK3:CLEAR
-- clear IACK3 counter
SENSE:VXI:IACK4:CLEAR
-- clear IACK4 counter
SENSE:VXI:IACK5:CLEAR
-- clear IACK5 counter
SENSE:VXI:IACK6:CLEAR
-- clear IACK6 counter
SENSE:VXI:IACK7:CLEAR
-- clear IACK7 counter
This command is meaningful only if the specified event is
presently being monitored. If, for example, the IACK3 line is
presently being monitored (because a
“SENSE:VXI:IACK3:LIMIT” command was executed), then
clearing the counter for the BERR event will have no effect.
Generating an
Interrupt When an
Alarm Condition is
Detected
The previous paragraphs have described how to program
tolerance limits. When one of the attributes monitored by the
EMS exceeds its tolerance limits, an alarm condition exists. The
following paragraphs describe how to program the EMS to
generate an interrupt when it detects an alarm condition.
The EMS uses the SCPI-defined mechanism for generating
interrupts based on out-of-tolerance conditions. The EMS
implements a 3-level hierarchy of status registers to provide for
enabling and disabling of interrupts based upon the individual
VXI attributes monitored.
At the highest level, a separate condition, event, and enable
register is maintained for each of the following attributes:
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