1261B User Manual
Racal Instruments
Ó
1995
Using The Enhanced Monitoring System 4-43
*STB? Query
This query reads the value of the “Status Byte”. Each bit of this
register indicates a true/false status condition. When the bit is
set, the condition is TRUE; when the bit is cleared, the condition
is FALSE. The bit assignments are defined by the IEEE-488.2
specification. The bit assignments are as follows:
Bit 0 -
Not used. Always returns 0.
Bit 1 -
Not used. Always returns 0.
Bit 2 -
Not used. Always returns 0.
Bit 3 -
Set when the SCPI “Questionable
Condition Register” ANDed with the SCPI
“Questionable Condition Enable Register”
is non-zero.
Bit 4 -
Message Available (MAV). Set when
there is a reply in the output buffer to be
read.
Bit 5 -
Extended Status Byte (ESB). Set when
the IEEE-488.2 Standard Event Register
ANDed with the IEEE-488.2 Standard
Event Status Register is non-zero.
Bit 6 -
Master Summary Status (MSS). Set when
the value of the Status Byte ANDed with
the value of the Service Request Enable
Register is non-zero. When this bit
transitions from a 0 to a 1, a Request True
interrupt is generated. When this bit
transitions from a 1 to a 0, a Request
False interrupt is generated.
Bit 7 -
Not used. Always returns 0.
*OPC Command
The *OPC command will cause the Operation Complete bit of
the Standard Event Status Register (SESR) to be set when the
command is executed. This is bit 0 of the SESR. The value of
the SESR may be read using the *ESR? query.
The *OPC command has no parameters. The only valid syntax
for this command is:
*OPC
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
