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1256E User Manual
Racal Instruments
©
2002
SCPI Command Basics 5-11
known as the “Event Summary Bit”, or ESB.
For example, if the PON and QYE bits of the
Standard Event
Status Register
are set, but the
Standard Event Status Enable
Register
value is 0, then the ESB of the
Status Byte Register
will
not be set. If either, or both, bits 7 and bit 2 of the
Standard Event
Status Enable Register
are set, then the ESB bit of the
Status Byte
Register
will be set.
Another way of viewing the
Standard Event Status Enable Register
is that it selects which conditions reflected in the
Standard Event
Status Register
are enabled to set the ESB bit of the status byte.
The
Status Byte Register
is similar to the
Standard Event Status
Register
. Each bit of this register reflects the true or false condition
of the corresponding bit. These bits reflect the PRESENT value of
the condition, whereas
the Standard Event Status Register
bits are
latched. That is, once a bit in the
Standard Event Status Register
is set, it remains set until a *CLS command is executed or an
*ESR? Query is executed. However, the bits of the
Status Byte
Register
change states as the corresponding condition becomes
true or false. These bits are NOT latched.
Also, the Status Byte is not cleared by reading the register. Each
bit of the Status Byte remains set until the condition indicated by
the bit is no longer present.
The following bits are assigned in the
Status Byte Register
. All
other bits are not used and will return “0" when read with the
*STB? query:
OSE Operation Status Event
Bit 7, bit weight = 128 decimal = 80 hexadecimal
This bit is set when any of the bits of the Operation
Status Event Register
are set. (This bit is NOT
shown on the diagram. For a description of the
Operation Status Event Register
, consult the “
SCPI
Status Registers
” section of this chapter.
MSS Master Summary Status.
Bit 6, bit weight = 64 decimal = 40 hexadecimal
This bit is set when one or more of the “enabled”
bits of the Status Byte are set. In other words:
SERVICE Register
(Status Byte bit 0 AND SRE bit 0)