1256E User Manual
SCPI Command Basics 5-12
Racal Instruments
©
2002
ENABLE Register
OR
(Status Byte bit 1 AND SRE bit 1)
OR
(Status Byte bit 2 AND SRE bit 2)
OR
(Status Byte bit 3 AND SRE bit 3)
OR
(Status Byte bit 4 AND SRE bit 4)
OR
(Status Byte bit 5 AND SRE bit 5)
OR
(Status Byte bit 7 AND SRE bit 7)
where the SRE is the
Service Request Enable Register
.
ESB
Event Summary Bit
Bit 5, bit weight = 32 decimal = 20 hexadecimal
This bit is set when one of the
enabled Standard
Event Status Enable Register
bits is set. The previous
paragraphs describe the formation of the ESB bit.
MAV
Message
Available
Bit 4, bit weight = 16 decimal = 10 hexadecimal
This bit is set when there is a message in the output
buffer of the 1256
All other bits (3, 2, 1, and 0) of the Status Byte are not assigned
and will always return 0.
When the MSS transitions from a 0 to a 1, the GPIB SRQ interrupt
is generated. The MSS will remain 1 until all enabled bits of the
Status Byte have returned to 0.
The
Service Request Enable
Register
is used to individually
enable bits in the Status Byte to set the MSS bit of the Status Byte,
thereby generating an interrupt. When the bit of the Service
Request Enable bit is set, and the corresponding bit of the
Status
Byte Register
is set, then the MSS bit will be a 1.
The following IEEE-488.2 Common Commands relate to the Status
Reporting Model:
