PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
In the Sol-20, the S-100 Bus structure takes the form of a
five-slot backplane board. It consists of a printed circuit board
with 100 lines (50 on each side) and five edge connectors on which
like-numbered pins are connected from one connector to another.
Functionally, the Sol version of the S-100 Bus is comprised of:
1. Sixteen output address lines from the CPU which are input
to all external memory and I/O circuitry. (Direct memory
access (DMA) devices must generate addresses on these
lines for DMA transfers.)
2. Eight data input/output lines that transfer data between
external memory and I/O devices and the CPU or DMA de-
vices. (These eight lines are paralleled with eight
other bus lines.)
3. Eight status output lines from the CPU support logic:
Memory and I/O devices use status signals to obtain in-
formation concerning the nature of the CPU cycle. (DMA
devices must generate these signals for DMA transfers.)
4. Nine processor command and control lines: Six of these
are output signals from the CPU support logic; three of
them are input signals to the CPU support logic from
memory and I/O devices. (In a DMA transfer, the DMA de-
vice assumes control of these lines.)
5. Five disable lines: Four of these are supplied by a DMA
device to disable the tri-state drivers on the CPU out-
puts during DMA transfers. The fifth is a derivative of
the DBIN output from the CPU, and it is used to disable
any memory addressed in Page ft. Use of this disable is
optional with a jumper.
6. Two input lines to the CPU support logic which are used
for requesting a wait period. One is used by memory and
I/O devices and the other by external devices.
7. Six power supply lines which supply power to expansion
modules.
8. Three clock lines.
9. Four special purpose signal lines.
10. Thirty-one unused lines.
Definitions for each S-100 Bus line, as used in the Sol, are
provided on Pages AVII-3 through AVII-6 in Appendix VII.
In addition to the S-100 Bus structure, Sol also uses an
eight-line keyboard input port, an eight-line parallel input port,
VIII-2
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