Processor Technology Sol-PC, Manual

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
interrupt operation. To prevent this, SINTA is inverted in U58 to 1)
disable U34 on pin 6 and 2) force pin 8 of NAND gate U23 high to dis-
able U35 and U36 on pin 5. (This feature is provided to enable fu-
ture versions of Sol to operate with a vectored interrupt system.)
8.5.3 Input/Output
Refer to the Input/Output Schematic In Section X, Page X-17.
This section in the Sol has five functional circuits: 1)
Parallel I/O Logic, 2) Sense Switch Logic, 3) Keyboard Flag Logic,
4) SDI/UART and 5) Baud Rate Generator.
The PP uses U95 and 96 (4-bit D-type registers) and their re-
lated logic. Data output to the PP connector (J2) is latched from
DIO0-7 by U95 and U96. Data is strobed into these registers on the
leading edge of an inverted active !PORT_OUT_FD signal on pin 4 of in-
verter U54. This strobe is also applied to pin 2 of U73 which func-
tions as a J-K flip-flop that is clocked by !
φ
2. When the !
φ
2 goes
from low to high 200 to 300 nsec after !PORT_OUT_FD, pin 7 of U73 goes
low to become !POL on pin 17 of J2. (This delay allows U95 and 96 to
stabilize.) U73 is reset in the middle of the following PSYNC which
means !P0L is active for the balance of the cycle.
The outputs of U95 and 96 are tri-state outputs that are ena-
bled by a low on pin 2. In the absence of POE at pin 15 of J2, pin 2
of U95 and 96 are low by virtue of the output on pin 8 of inverter U55.
Note that the input to U55 is normally pulled up through R63. The POE
provision permits tri-stating an external bidirectional data bus.
As discussed in Paragraph 8.5.1, parallel input data on J2 is
fed directly to the Data Input Multiplexer (see Page X-15). The
strobe that indicates the presence of input data, !PDR on pin 4 of J2,
is applied to pins 2 and 3 of one section in U72, a J-!K flip-flop
which is connected as a D flip-flop. When !PDR goes active (low), pin
7 of U72 will go high on the next low-to-high transition of
φ
2 to
toggle the following U72 stage. At this point pins 9 and 10 of the
second section in U72 go high and low respectively. Pin 9 supplies
PIAK on pin 5 of J2. When high, PIAK signals the external device
that Sol has yet to complete acceptance of the data. The state of
pin 10 of U72 is transmitted to INT1 of the Internal Data Bus through
a U71 tri-state noninverting buffer. U71 is enabled only for the
duration of !PORT_IN_FA (auxiliary status). During the time U71 is
enabled, the CPU reads the Internal Data Bus. A high INT1 indicates
the parallel input data is not ready; a low indicates the data is
ready.
The second U72 flip-flop is preset by !PORT_IN_FD or POC.
!PORT_IN_FD is active to read data in from the PP; POC occurs only
when Sol is restarted or power is turned on. Thus the PP is reset
and ready for another transfer at the end of a transfer or when POC
is active.
VIII-18