7 Operating Instructions
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7-3
That is why, in the 5017 a PLL circuit (Phase Locked Loop) is used to synchronize
the measurement time with the period of the main line frequency. An integer multiple
of the mains period is always contained in the measurement time.
Due to the fully integrating measurement process, the positive and negative half-
waves of line voltage are neutralized. Line scatter can thereby be completely sup-
pressed.
The 5017 achieves a Series Mode Suppression of >100 dB with line frequencies of
50 / 60Hz ± 5%.
Common Mode Suppression
The ability of a measurement device, to display only the desired differential signal
between the “HI” and “LO” inputs, while suppressing an equal voltage on both
clamps against ground, is designated as Common Mode Suppression. In an ideal
system, no errors would be generated, but in real life, scatter capacitances, isolation
resistances, and non-symmetrical resistances convert a part of the common mode
voltage into a series voltage.
Common mode suppression in the 5017 is more than 160dB, with a non-symmetry of
1kOhm in the leads.
Thermal Voltages
One of the most common error sources in DC Voltage measurement in the low signal
range is the thermal voltage produced by thermal EMF.
These thermal voltages occur at the contact points of different metals that are at the
same or different temperature levels.
Diagram: Thermal Voltage sources in a measurement circuit
