Pioneer PDP-501MX, Service Manual

Page: 70 / 96

PDP-501MX, PDP-V501X
70
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
VDD 6
VSS 6
YUV D3
YUV D4
YUV D5
YUV D6
YUV D7
VDD 7
VSS 7
SNRST
SNDA
SNCL
AUX
Ho
NC
NC
YUV A7
YUV A6
YUV A5
YUV A4
YUV A3
YUV A2
VSS 8
VDD 8
YUV A1
YUV A0
YUV A11
YUV A10
YUV A9
YUV A8
TYPE
S
G
O
O
O
O
O
S
G
I
I/O
I
O
O
-
-
I
I
I
I
I
I
G
S
I
I
I
I
I
I
Pin Function
Supply voltage 6
Ground 6
Y bit 3
Y bit 4
Y bit 5
Y bit 6
Y bit 7
Supply voltage 7
Ground 7
Field frequent reset from microcontroller;reset for SNERT interface
Data for SNERT interface
Clock for SNERT interface
Spre output form line-sequencer
Output hold to e.g.LC.display
Not connected
Not connected
Y bit 7 from FM1
Y bit 6 from FM1
Y bit 5 from FM1
Y bit 4 from FM1
Y bit 3 from FM1
Y bit 2 from FM1
Ground 8
Supply voltage 8
Y bit 1 from FM1
Y bit 0 from FM1
UV bit 3 from FM1
UV bit 2 from FM1
UV bit 1 from FM1
UV bit 0 from FM1
1 2 3 4 5 6
7
8
9
10
11
12
13
14
15
16
17
18 19 20
21 22
23 24 25
26
27 28
29
30
31
32
33
34
35
36
37
38
39
40 41 42 43 44
UV3
UV4
UV5
UV6
UV7
Y0
Y2
Y1
Y3
Y
(B - Y)
(R - Y)
SDA
UV2 UV1 UV0 SUB
C
Y
C
UV
V
DDA
V
DDA3
REFL
Y
REFL
UV
CUR
Y4 Y5 Y6 Y7 AP
SP
MC
LLC
HREF
RESET
SCL
V
DDD1
V SSD1
V
SSA3
V DDA2
V
SSA2
V
SSA1
V
DDA1
V DDD2
V
SSD2
SAA7165
1
2
3
12
13 22 23
24
26
30
31 32
33
34 35
36
37
38
40 41 42
43
44
V DDD1 V DDD2 V DDA1 V DDA2 V DDA3 CUR V DDA4
MC
LLC
HREF
RESET
SCL
SDA
I
2
C-bus
Y7 to Y0
UV7 to
UN0
YUV-bus
V
SSD1
V
SSD2
AP SP SUB V
SSA1
V
SSA2
V
SSA3
C
Y
Y
REFL
Y
(B - Y)
REFL UV
C UV
(R - Y)
DAC 3
DAC 2
DAC 1
DATA
SWITCH
SAA7165
DCTI
Y
U
V
PEAKING
AND
CORING
INTERPOLATION
FILTER
Y
FORMATTER
UV
FORMATTER
TIMING
CONTROL
I
2
C-BUS
CONTROL
TEST
CONTROL
21 to 14
11 to 4
data clock
8
8
25
27
28
29
25
25
39
25
7
ASAA7165WP
(PROGRESSIVE BLOCK : IC4702)
VIDEO ENHANCEMENT D/A
¶
Pin Assignment
¶
Block Diagram