52
DJM-850-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
• Pin Function
Pin
N
o. Pin
N
ame
I/O
Function and Operation
A01
V
SS G
V
SS (Ground)
A02
PF9/PPI D9/RSCLK1/xSPISEL6
I
Bit clock for receive (CH3, CH4)
A03
PF11/PPI D11/TFS1/CZM
I
LR clock for transmission (CH3, CH4)
A04 SCL
I/O
N
ot used
A05
PF13/PPI D13/TSCLK1/xSPISEL3/CUD
I
Bit clock for transmission (CH3, CH4)
A06
PF15/PPI D15/DR1SEC/UART1RX/TACI3
I
Audio input (CH4)
A07 PH0/
N
D_D0/HOST_D0 I
N
ot used
A0
8
PH2/
N
D_D2/HOST_D2 I
N
ot used
A09 PH4/
N
D_D4/HOST_D4 I
N
ot used
A10 XTAL
O Clock
output
A11 CLKI
N
I
Clock
input
A12 PH
8
/xSPISEL4/HOST_D
8
/TACLK2 I
N
ot used
A13 PH10/x
N
D_CE/HOST_D10 I
N
ot used
A14
RTXI
I
Real time clock input
A15 RTXO
O
N
ot used
A16
V
DDRTC
V
Power supply for real time clock
A17
V
SS G
V
SS (Ground)
A1
8
USB_XO
O
USB clock output
A19
USB_XI
I
USB clock input
A20
V
SS G
V
SS (Ground)
B01 PF7/PPI
D7/DR0SEC/
N
D_D7A/TACI1
I
Audio input (CH2)
B02 PF
8
/PPI D
8
/DR1PRI
I
Audio input (CH3)
B03
PF10/PPI D10/RFS1/xSPISEL7
I
LR clock for receive (CH3, CH4)
B04 SDA
I/O
N
ot used
B05
PF12/PPI D12/DT1PRI/xSPISEL2/CDG
O
Audio output (CH3)
B06
PF14/PPI D14/DT1SEC/UART1TX
O
Audio output (CH4)
B07 PH1/
N
D_D1/HOST_D1 I
N
ot used
B0
8
PH3/
N
D_D3/HOST_D3 I
N
ot used
B09 PH5/
N
D_D5/HOST_D5 I
N
ot used
B10 PH6/
N
D_D6/HOST_D6 I
N
ot used
B11 PH7/
N
D_D7/HOST_D7 I
N
ot used
B12 PH9/xSPISEL5/HOST_D9/TACLK3
I
N
ot used
B13 PH11/x
N
D_
W
E/HOST_D11 I
N
ot used
B14 PH12/x
N
D_RE/HOST_D12 I
N
ot used
B15 PH13/x
N
D_BUSY/HOST_D13 I
N
ot used
B16 PH14/
N
D_CLE/HOST_D14 I
N
ot used
B17 PH15/
N
D_ALE/HOST_D15 I
N
ot used
B1
8
RESET~
I Reset
B19
N
MI~ I
N
on-Maskable interrupt
B20
V
SS G
V
SS (Ground)
C01 PF5/PPI
D5/TSCLK0/
N
D_D5A/TACLK1
I
Bit clock for transmission (CH1, CH2)
C02 PF6/PPI
D6/DT0SEC/
N
D_D6A/TACI0
O
Audio output (CH2)
C19 CLKBUF
O Clock
buffer
C20
USB_ID
I
USB mode judgment
D01 PF3/PPI
D3/DT0PRI/
N
D_D3A
O
Audio output (CH1)
D02 PF4/PPI
D4/TFS0/
N
D_D4A/TACLK0
I
LR clock for transmission (CH1, CH2)
D19
V
DDUSB
V
3.3
V
USB reference voltage
D20
USB_RSET
I
USB OTG setting
E01 PF1/PPI
D1/RFS0/
N
D_D1A
I
LR clock for receive (CH1, CH2)
E02 PF2/PPI
D2/RSCLK0/
N
D_D2A
I
Bit clock for receive (CH1, CH2)
E19 USB_
V
BUS I
5
V
voltage for USB
E20
USB_DP
I/O
USB data line (Differ)
F01
PF0/PPI D0/DR0PRI /
N
D_D0A
I
Audio input (CH1)
F02 PPI_FS1/TMR0
O
N
ot used
F19
V
DDEXT
V
Power supply voltage for I/O
F20
USB_DM
I/O
USB data line (Differential -)
G01 PG15/TFS0A/HOST_CE
I
USB_RC
V
: UART receive information (MAI
N
)
G02 PPI_CLK/TMRCLK
I
N
ot used
G07
V
DDEXT
V
Power supply voltage for I/O
ADSP-BF525BBCZ-5A (MAIN ASSY: IC2603)
USB UCOM