Pioneer DJM-850-K, Service Manual

Page: 47 / 203

47
DJM-850-K
5 6 7 8
5 6 7 8
A
B
C
D
E
F
D 8 10K013BZKB400 (MAIN ASSY: IC3201)
DSP
• Pin Function
Pin N o. Pin N ame I/O Function and Operation
A1 V ss G G N D
A2 V ss G G N D
A3 V ss G G N D
A4 AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] I McASP0 receive master clock
A5 AXR0[11]/AXR2[0]/GP3[11] O N ot used (open)
A6 AXR0[7]/MDIO_CLK/GP3[7] I CH1 A N ALOG I N
A7 AXR0[3]/RMII_CRS_D V /AXR2[2]/GP3[7] I RETUR N I N
A 8 EMB_RAS O SDRAM connection
A9 EMB_A[10]/GP7[12] O SDRAM address
A10 EMB_A[3]/GP7[5] O SDRAM address
A11 EMB_A[7]/GP7[9] O SDRAM address
A12 EMB_ W E_DQM[3] O N ot used (open)
A13 EMB_D[24] O N ot used (open)
A14 EMB_D[26] O N ot used (open)
A15 V ss G G N D
A16 V ss G G N D
B1 RS V 2 V Power supply 1.2 V
B2 V ss G G N D
B3 V ss G G N D
B4 ACLKR0/ECAP1/AP W M1/GP2[15] I McASP0 receive bit clock
B5 AHCLKX0/AHCLKX2/USB_REFCLKI N /GP2[11] I McASP0 transmit master clock
B6 AXR0[ 8 ]/MDIO_D/GP3[ 8 ] I CH3 A N ALOG I N
B7 AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] I MIC I N
B 8 AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] I CH2 A N ALOG I N
B9 EMB_BA[1]/GP7[0] O SDRAM bank address
B10 EMB_A[2]/GP7[4] O SDRAM address
B11 EMB_A[6]/GP7[ 8 ] O SDRAM address
B12 EMB_A[11]/GP7[13] O SDRAM address
B13 EMB_ W E_DQM[2] O N ot used (open)
B14 EMB_D[25] O N ot used (open)
B15 EMB_A[12]/GP3[13] O SDRAM address
B16 D V DD V Power supply 3.3 V
C1 USB1_ V DDA33 N ot used (open)
C2 USB1_ V DDA1 8 N ot used (open)
C3 USB0_ V DDA12 G N D
C4 AFSR0/GP3[12] I McASP0 receive frame sync
C5 ACLKX0/ECAP0/AP W M0/GP2[12] I McASP0 transmit bit clock
C6 UART1_RXD/AXR0[9]/GP3[9] I CH4 A N ALOG I N
C7 AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] I CH3 USB I N
C 8 AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] I CH1 USB I N
C9 EMB_BA[0]/GP7[1] O SDRAM bank address
C10 EMB_A[1]/GP7[3] O SDRAM address
C11 EMB_A[5]/GP7[7] O SDRAM address
C12 EMB_A[9]/GP7[11] O SDRAM address
C13 EMB_SDCKE O SDRAM connection
C14 EMB_CLK O SDRAM clock
C15 EMB_ W E_DQM[1]/GP5[14] O SDRAM connection
C16 EMB_D[ 8 ]/GP6[ 8 ] I/O SDRAM data bus
D1 PLL0_ V DDA V Power supply 1.2 V
D2 USB0_ID G N ot used (open)
D3 USB0_ V BUS G N ot used (open)
D4 AMUTE1/EHRP W MTZ/GP4[14] O N ot used (open)
D5 AFSX0/GP2[13]/BOOT[10] I McASP0 transmit frame sync
D6 UART1_TXD/AXR0[10]/GP3[10] O N ot used (open)
D7 AXR0[6]/RMII_RXER/ACLKR2/GP3[6] I CH2 USB I N
D 8 AXR0[2]/RMII_TXE N /AXR2[3]/GP3[2] I CH4 USB I N
D9 EMB_CS[0] O SDRAM chip select
D10 EMB_A[0]/GP7[2] O SDRAM address
D11 EMB_A[4]/GP7[6] O SDRAM address