50
DJM-850-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
• Pin Function
Pin
N
o. Pin
N
ame
I/O
Function and Operation
M2 AXR1[
8
]/EP
W
M1A/GP4[
8
]
O
MASTER L OUT
M3 AXR1[7]/EP
W
M1B/GP4[7]
O
USB CH4 OUT
M4 AXR1[6]/EP
W
M2A/GP4[6]
O
USB CH1 OUT
M5 D
V
DD
V
Power supply 3.3
V
M6
V
ss G
G
N
D
M7
V
ss G
G
N
D
M
8
D
V
DD
V
Power supply 3.3
V
M9 D
V
DD
V
Power supply 3.3
V
M10
V
ss G
G
N
D
M11
V
ss G
G
N
D
M12 D
V
DD
V
Power supply 3.3
V
M13 EMA_
W
E/UHPI_UR
W
/AXR0[12]/GP2[3]/BOOT[14] O
FPGA
connection
M14 EMA_
W
E_DQM[0]/UHPI_HI
N
T/AXR0[15]/GP2[9] O
N
ot used (open)
M15
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
I/O
External data bus
M16
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
I/O
External data bus
N
1 AXR1[5]/EP
W
M2B/GP4[5]
O
MASTER R OUT
N
2 AXR1[4]/EQEP1B/GP4[4]
O REC
OUT
N
3
AXR1[10]/GP5[10]
O
USB CH2 OUT
N
4
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
O
SPI CHIP SELECT
N
5 SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
O
N
ot used (open)
N
6 EMA_
W
AIT[0]/UHPI_HRDY/GP2[10]
I
PULL UP (3.3
V
)
N
7 EMA_RAS/EMA_CS[5]/GP2[2]
O
N
ot used (open)
N8
EMA_A[10]/LCD_
V
SY
N
C/GP1[10] O
N
ot used (open)
N
9
EMA_A[3]/LCD_D[6]/GP1[3]
O
External data bus
N
10
EMA_A[7]/LCD_D[0]/GP1[7]
O
External data bus
N
11 EMA_A[12]/LCD_MCLK/GP1[12]
O
N
ot used (open)
N
12 EMA_D[
8
]/UHPI_HD[
8
]/LCD_D[
8
]/GP0[
8
]
I/O
External data bus
N
13
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
I/O
External data bus
N
14
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
I/O
External data bus
N
15
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
I/O
External data bus
N
16
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
I/O
External data bus
P1 AXR1[3]/EQEP1A/GP4[3]
O BOOTH
OUT
P2 AXR1[2]/GP4[2]
O DIGITAL
OUT
P3 UART0_TXD/I2C0_SCL/TM640_OUT12/GP5[9]/BOOT[9]
O
N
ot used (open)
P4 SPI1_SCS[0]/UART2_TXD/GP5[13]
O
N
ot used (open)
P5 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
O
N
ot used (open)
P6 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
O BOOT mode setting/ For SPI communication
P7 EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
O
N
ot used (open)
P
8
EMA_BA[1]/LCD_D[5]/UHPI_HH
W
L/GP1[13] O
External
address
P9 EMA_A[2]/MMCSD_CMD/UHPI_HC
N
TL1/GP1[2] O
External
address
P10 EMA_A[6]/LCD_D[1]/GP1[6]
O External
address
P11 EMA_A[11]/LCD_AC_E
N
B_CS/GP1[11] O
N
ot used (open)
P12 EMA_
W
E_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[
8
] O
N
ot used (open)
P13
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
I/O
External data bus
P14
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
I/O
External data bus
P15
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
I/O
External data bus
P16
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
I/O
External data bus
R1 D
V
DD
V
Power supply 3.3
V
R2
AXR1[1]/GP4[1]
O
USB CH3 OUT
R3 UART0_RXD/I2C0_SDA/TIM64P0_I
N
12/GP5[
8
]/BOOT[
8
] O
N
ot used (open)
R4 SPI1_E
N
A/UART2_RXD/GP5[12] O
For DSP processing cycle measurement
R5 SPI0_E
N
A/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
O
For SPI communication
R6 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
I BOOT mode setting/ For SPI communication
R7 EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
O FPGA
connection
R
8
EMA_BA[0]/LCD_D[4]/GP1[14]
O
N
ot used (open)
R9 EMA_A[1]/MMCSD_CLK/UHPI_HC
N
TL0/GP1[1] O
External
address
R10 EMA_A[5]/LCD_D[2]/GP1[5]
O External
address
R11 EMA_A[9]/LCD_HSY
N
C/GP1[9] O
External
address
R12 EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
O
N
ot used (open)