146
DJM-850-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
10.25 MAIN ASSY (19/19)
1 0 u / 1 6
C 6 0 9
1 0 u / 1 6
C 6 0
8
C604
0.1u/10
C 6 0 5
1 0 0 0 p / 5 0
C601
0.01u/16
C603
0.1u/10
C 6 0 2
D C H 1 2 0 1 - A
1 0 u
1 0
V
C607
DCH1201-A
10u
10
V
C 6 0 6
0 . 0 1 u / 1 6
G
N
D D
G
N
D D
G
N
D A _ D A
G
N
D D
A K 4 3
8
7 E T
I C 6 0 1
M C L K
1
B I C K
2
S D T I
3
L R C K
4
5 RST
N
6 CS
N
7 CCLK
8
C D T I
9
N
C
1 0
A O U T R
1 1
A O U T L
1 2
V
C O M
1 3
V
S S
1 4
A
V
D D
1 5
D
V
D D
1 6
D Z F
R 6 0 7
1 0 k
2
1
4
3
6
5
8
7
R 6 0 9
0
R 6 0 4
0
R 6 0 6
1 0 0
R 6 0
8
0
R 6 1
3 . 3 k
( D )
R 6 0 5
0
R 6 1 0
1 0
R 6 1 2
3 . 3 k
( D )
R 6 0 1
0
V
+ 5 A _ O
6 M _ C L K _ D A
1 1 : 2 K ; 1 5 : 2 B
D A _ R E S E T
1 0 : 1 3 C ; 1 5 : 2 C
9 6 k _ C L K _ D A
1 1 : 2 K ; 1 5 : 2 B
2 4 M _ C L K _ D A
1 1 : 2 K ; 1 5 : 2 C
M U T E
1 : 9 B ; 1 5 : 3 F ; 1 6 : 7 E ; 1 7 : 2 H ; 1
8
: 2 D
A D A T _ S E
N
D
1 3 : 1 5 I
SE
N
D_DAC
SE
N
D
R S 1 / 1 0 S R * * * J
F
C C S Q C H * * * J
R S 1 / 1 6 S S * * * J
F
N
O T E S
F
C E
V W
* * * M
C K S Q Y B * * * K
i s S T B Y
H
V W
S Q
C E
V W N
P * * * M
F
F
R S 1 / 1 0 S R * * * * D
H
V
A
W
F
C C S S C H * * * D
S R ( D )
C K S S Y B * * * K
N
M
R A B 4 C Q * * * J
F
F
C C S R C H * * * J
C E A
N
P * * * M
S R
C F H X S Q
N
P
C E H
V W
* * * M
C E H
V
A
W
* * * M
+
F
R S 1 /
8
S Q * * * J
( D )
S R
S A
C H ( D )
C K S R Y B * * * K
S Q C H
+
C H
C C S S C H * * * J
R S 1 / 1 6 S S * * * * D
R
N
1 / 1 6 S E * * * * D
S Q
R S 1 / 4 S A * * * J
F
C E A
N
P
C F H X S Q * * * J
+
S R C H
F
F
F
R
N
From FPGA
From MAI
N
_UCOM
From FPGA
From DSP
From OUTPUT IF
D
19/19
D
11/19,15/19
D
10/19,15/19
D
13/19
D
1/19,15/19-1
8
/19
: SE
N
D OUT Digital Signal
(SE
N
D D)
: SE
N
D OUT Signal (L ch)
(SE
N
D)
(SE
N
D D)
(SE
N
D)
(SE
N
D)
1-77 1-73
1-76
1-75 1-74
1-72