Pioneer DJM-1000, Service Manual

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DJM-1000
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No. Pin Name I/O Pin Function
TIMER 1
13 TOUT1/AXR0[4]/AXR1[11] O
Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z) or McASP1 TX/RX data pin 11
(I/O/Z).
12 TINP1/AHCLKX0 I Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z).
TIMER0
18 TOUT0/AXR0[2]/AXR1[13] O
Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z) or McASP1 TX/RX data pin 13
(I/O/Z).
17 TINP0/AXR0[3]/AXR1[12] I
Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z) or McASP1 TX/RX data pin 12
(I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
8 CLKS1/SCL1 I McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z).
36 CLKR1/AXR0[6]/AXR1[9] I/O/Z
McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z) or McASP1 TX/RX
data pin 9 (I/O/Z).
33 CLKX1/AMUTE0 I/O/Z McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
37 DR1/SDA1 I McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
32 DX1/AXR0[5]/AXR1[10] O/Z
McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z) or McASP1 TX/RX
data pin 10 (I/O/Z).
38 FSR1/AXR0[7]/AXR1[8] I/O/Z
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z) or McASP1
TX/RX data pin 8 (I/O/Z).
31 FSX1 I/O/Z McBSP1 transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
28 CLKS0/AHCLKR0 I
McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-
frequency master clock (I/O/Z).
19 CLKR0/ACLKR0 I/O/Z McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
16 CLKX0/ACLKX0 I/O/Z McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
27 DR0/AXR0[0]/AXR1[15] I
McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z) or McASP1 TX/RX data
pin 15 (I/O/Z).
20 DX0/AXR0[1]/AXR1[14] O/Z
McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z) or McASP1 TX/RX
data pin 14 (I/O/Z).
24 FSR0/AFSR0 I/O/Z
McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
21 FSX0/AFSX0 I/O/Z
McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
INTER-INTEGRATED CIRCUIT 1 (I2C1)
8 CLKS1/SCL1 I/O/Z McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z).
37 DR1/SDA1 I/O/Z McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
INTER-INTEGRATED CIRCUIT 0 (I2C0)
41 SCL0 I/O/Z I2C0 clock
42 SDA0 I/O/Z I2C0 data
GENERAL-PURPOSE INPUT/OUTPUT 0 (GP0)
174 HD15/GP0[15] I/O/Z Host-port data pin 15 (I/O/Z) [ default] or this pin can be programmed as a GP0 15 pin (I/O/Z).
173 HD14/GP0[14] I/O/Z
Host-port data pins (I/O/Z) [default] or general-purpose input/output 0 pins (I/O/Z) and some
function as boot configuration pins at reset.
• Used for transfer of data, address, and control
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors
172 HD13/GP0[13] I/O/Z
168 HD12/GP0[12] I/O/Z
167 HD11/GP0[11] I/O/Z
166 HD10/GP0[10] I/O/Z
165 HD9/GP0[9] I/O/Z
160 HD8/GP0[8] I/O/Z
7 GP0[7](EXT_INT7) I/O/Z General-purpose input/output 0 pins (I/O/Z) which also function as external interrupts [default]
• Edge-driven
• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
GP0[4] and GP0[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0
McASP0 mute input, respectively.
2 GP0[6](EXT_INT6) I/O/Z
6
GP0[5](EXT_INT5)/AMUTEIN0
I/O/Z
1 GP0[4](EXT_INT4)/AMUTEIN1 I/O/Z