Pioneer DJM-1000, Service Manual

Page: 141 / 168

DJM-1000
141
5 6 7 8
5 6
7
8
C
D
F
A
B
E
R0H R0L
I/O ports
Port P0
Watchdog timer
(15 bits)
D/A converter
(8 bits
×
2 channels)
A/D converter
(10 bits
×
8 channels)
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits
×
5 channels)
x/y converter
(16 bits
×
16 bits)
CRC arithmetic circuit (CCITT)
(Polynomial: X
16
+X
12
+X
5
+1)
Internal peripheral finctions
Timer
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
System clock generator
XIN - XOUT
XCIN - XCOUT
Memory
Registers
M16C/80 series 16-bit CPU core
ROM
(Note 1)
RAM
(Note 2)
DRAM
controller
DRAM
controller
Multiplier
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
Port P7
Port P8
Port P85
Port P9
Port P10
8
Port P11 Port P12 Port P13 Port P14 Port P15
5 8 8 7 8
8
8
8
8
8 8 8 8 8 8
R0H R0L
R1H R1L
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
R2
R3
A0
A1
FB
SB
No. Pin Name I/O Pin Function
1
P96/ANEX1/TXD4/SDA4/SRxD4
I/O
8-bit I/O port P9 Pins in this port also function as UART3 and UART4 I/O pins, Timer B0-B4
input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input
pins as selected by software.
2 P95/ANEX0/CLK4 I/O
3
P94/DA1/TB4IN/CTS4/RTS4/SS4
I/O
4
P93/DA0/TB3IN/CTS3/RTS3/SS3
I/O
5
P92/TB2IN/TxD3/SDA3/SRxD3
I/O
6
P91/TB1IN/RxD3/SCL3/STxD3
I/O
7 P90/TB0IN/CLK3 I/O
8 P146 I/O 7-bit I/O port P14
9 P145 I/O 7-bit I/O port P14
10 P144 I/O 7-bit I/O port P14
11 P143 I/O 7-bit I/O port P14
12 P142 I/O 7-bit I/O port P14
13 P141 I/O 7-bit I/O port P14
14 P140 I/O 7-bit I/O port P14
15 BYTE I
External data bus width select A 16-bit width is selected when this input is "L"; an 8-bit width is
selected when this input is "H".
16 CNVSS I This pin switches between processor modes.
17 P87/XCIN I/O I/O port P8 / Input for sub clock generation circuit
18 P86/XCOUT I/O I/O port P8 / Output for sub clock generation circuit
19 RESET I Reset input L: Reset
20 XOUT O Main clock output
21 VSS
−
Ground (0V)
Block Diagram
Pin Function