Pioneer DJM-1000, Service Manual

Page: 150 / 168

DJM-1000
150
1 2 3 4
1 2 3 4
C
D
F
A
B
E
No. Pin Name I/O Pin Function
153 HAS/ACLKX1 I Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).
145 HCS/AXR0[13]/AXR1[2] I
Host chip select (I) [default] or McASP0 TX/RX pin 13 (I/O/Z) or McASP1 TX/RX pin 2 (I/O/Z).
151 HDS1/AXR0[9]/AXR1[6] I
Host data strobe 1 (I) [default] or McASP0 TX/RX pin 9 (I/O/Z) or McASP1 TX/RX pin 6 (I/O/Z).
150 HDS2/AXR0[10]/AXR1[5] I
Host data strobe 2 (I) [default] or McASP0 TX/RX pin 10 (I/O/Z) or McASP1 TX/RX pin 5 (I/O/Z).
140 HRDY/ACLKR1 O/Z Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
EMIF - COMMON SIGNALS TO ALL TYPES OF MEMORY
57 CE3 O/Z
Memory space enables
• Enabled by bits 28 through 31 of the word address
• Only one asserted during any external data access
61 CE2 O/Z
103 CE1 O/Z
102 CE0 O/Z
108 BE1 O/Z
Byte-enable control
• Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory
• Can be directly connected to SDRAM read and write mask signal (SDQM)
110 BE0 O/Z
EMIF - BUS ARBITRATION
137 HOLDA O/Z Hold-request-acknowledge to the host
138 HOLD I Hold request from the host
136 BUSREQ O/Z Bus request output
EMIF - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
78 ECLKIN I External EMIF input clock source
77 ECLKOUT O/Z
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]).
EKSRC = 0 - ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default).
EKSRC = 1 - ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN)
EKEN = 0 - ECLKOUT held low
EKEN = 1 - ECLKOUT enabled to clock (default)
79 ARE/SDCAS/SSADS O/Z Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
75 AOE/SDRAS/SSOE O/Z Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
83 AWE/SDWE/SSWE O/Z Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
56 ARDY I Asynchronous memory ready input
EMIF - ADDRESS
109 EA21 O/Z
External address ( word, half-word, and byte address) The EMIF adjusts the address based on
memory width:
Width Pins Address
32 21:2 21 through 2
16 21:2 20 through 1
8 21:2 19 through 0
101 EA20 O/Z
100 EA19 O/Z
95 EA18 O/Z
99 EA17 O/Z
92 EA16 O/Z
94 EA15 O/Z
90 EA14 O/Z
91 EA13 O/Z
93 EA12 O/Z
86 EA11 O/Z
76 EA10 O/Z
74 EA9 O/Z
71 EA8 O/Z
70 EA7 O/Z
69 EA6 O/Z
68 EA5 O/Z
64 EA4 O/Z
63 EA3 O/Z
62 EA2 O/Z