DJM-1000
151
5
6
7
8
5
6
7
8
C
D
F
A
B
E
No.
Pin Name
I/O
Pin Function
EMIF - DATA
112 ED15/GP1[15]
I/O/Z
External data pins The ED15 - ED0 pins are muxed with general-purpose input/output 1 (GP1)
pins. The EMIFDIS bit in the DEVCFG register controls the function of these muxed pins, EMIF
is degault.
113 ED14/GP1[14]
I/O/Z
111 ED13/GP1[13]
I/O/Z
118 ED12/GP1[12]
I/O/Z
117 ED11/GP1[11]
I/O/Z
120 ED10/GP1[10]
I/O/Z
119 ED9/GP1[9]
I/O/Z
123 ED8/GP1[8]
I/O/Z
122 ED7/GP1[7]
I/O/Z
121 ED6/GP1[6]
I/O/Z
128 ED5/GP1[5]
I/O/Z
127 ED4/GP1[4]
I/O/Z
129 ED3/GP1[3]
I/O/Z
130 ED2/GP1[2]
I/O/Z
131 ED1/GP1[1]
I/O/Z
132 ED0/GP1[0]
I/O/Z
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)
1
GP0[4](EXT_INT4)/AMUTEIN1
I/O/Z General-purpose input/output 0 pin 4 and external interrupt 4 (I/O/Z) [default] or McASP1 mute input (I/O/Z).
154 HD3/AMUTE1
I/O/Z Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
140 HRDY/ACLKR1
I/O/Z Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
161 HD6/AHCLKR1
I/O/Z Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z).
153 HAS/ACLKX1
I/O/Z Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).
159 HD5/AHCLKX1
I/O/Z Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z).
139 HHWIL/AFSR1
I/O/Z
Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or
McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z).
155 HD2/AFSX1
I/O/Z
Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK)
(I/O/Z).
27
DR0/AXR0[0]/AXR1[15]
I/O/Z
McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z) or McASP1 TX/RX data
pin 15 (I/O/Z).
20
DX0/AXR0[1]/AXR1[14]
I/O/Z
McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z) or McASP1 TX/RX
data pin 14 (I/O/Z).
18
TOUT0/AXR0[2]/AXR1[13]
I/O/Z
Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z) or McASP1 TX/RX data pin 13
(I/O/Z).
17
TINP0/AXR0[3]/AXR1[12]
I/O/Z
Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z) or McASP1 TX/RX data pin 12
(I/O/Z).
13
TOUT1/AXR0[4]/AXR1[11]
I/O/Z
Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z) or McASP1 TX/RX data pin 11
(I/O/Z).
32
DX1/AXR0[5]/AXR1[10]
I/O/Z
McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z) or McASP1 TX/RX
data pin 10 (I/O/Z).
36
CLKR1/AXR0[6]/AXR1[9]
I/O/Z
McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z) or McASP1 TX/RX
data pin 9 (I/O/Z).
38
FSR1/AXR0[7]/AXR1[8]
I/O/Z
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z) or McASP1
TX/RX data pin 8 (I/O/Z).
152 HD1/AXR0[8]/AXR1[7]
I/O/Z
Host-port data pin 1 (I/O/Z) [ default] or McASP0 TX/RX data pin 8 (I/O/Z) or McASP1 TX/RX
data pin 7 (I/O/Z).
151 HDS1/AXR0[9]/AXR1[6]
I/O/Z
Host data strobe 1 (I) [default] or McASP0 TX/RX data pin 9 (I/O/Z) or McASP1 TX/RX data pin
6 (I/O/Z).
150 HDS2/AXR0[10]/AXR1[5]
I/O/Z
Host data strobe 2 (I) [default] or McASP0 TX/RX data pin 10 (I/O/Z) or McASP1 TX/RX data
pin 5 (I/O/Z).
147 HD0/AXR0[11]/AXR1[4]
I/O/Z
Host-port data pin 0 (I/O/Z) [ default] or McASP0 TX/RX data pin 11 (I/O/Z) or McASP1 TX/RX
data pin 4 (I/O/Z).
Summary of Contents for DJM-1000
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