Pioneer DJM-1000, Service Manual

Page: 159 / 168

DJM-1000
159
5 6 7 8
5 6
7
8
C
D
F
A
B
E
• Advanced Multi-Bit 96kHz 24bit
∆∑
DAC
DVSS 1
LRCK
CKS2 28
DVDD 2 CKS1 27
MCLK 3 CKS0 26
PDN 4 P/S 25
BICK 5 VCOM 24
SDATA 6 AOUTL+ 23
LRCK 7 AOUTL- 22
SMUTE/CSN 8 AOUTR+ 21
DFS 9 AOUTR- 20
DEM0/CCLK 10 AVSS 19
DEM1/CDTI 11 AVDD 18
DIF0 12 VREFH 17
DIF1 13 VREFL 16
DIF2 14 BVSS
15
Audio Data
Interface
De-emphasis
Soft Mute
De-emphasis
Control
8
×
Interpolator
7
AOUTL+
23
BVSS 15
DIF0
BICK
5
SDATA
6
∆∑
Modulator
SCF
VCOM 24
AOUTL-
22
8
×
Interpolator
AOUTR+
AOUTR-
21 ∆∑
Modulator
SCF
20
SMUTE 8
DFS 9
PDN
De-emphasis
Soft Mute
Control
Register
4
12
DIF1
13
DIF2
14
DEM0
10
DEM1
11
DVDD
2
DVSS
1
AVDD
18
AVSS
19
CSN
8
CCLK
10
CDTI
11 25
P/S
Clock
Divider
MCLK
3
CKS0
26
CKS1 VREFH
VREFL
27 28 17 16
CKS2
No. Pin Name I/O Pin Function No. Pin Name I/O Pin Function
1 DVSS
Digital Ground Pin
14 DIF2 I
Digital Input Format Pin
2 DVDD Digital Power Supply Pin, 3.3V or 5.0V 15 BVSS
−
−
−
Substrate Ground Pin, 0V
3 MCLK I
Master Clock Input Pin
16 VREFL I
Low Level Voltage Reference Input Pin
4 PDN I
Power-Down Mode Pin When at "L", the
AK4393 is in power-down mode and is
held in reset. The AK4393 should always
be reset upon power-up.
17 VREFH I
High Level Voltage Reference Input Pin
5 BICK I
Audio Serial Data Clock Pin The clock of
64fs or more than is recommended to be
input on this pin.
18 AVDD
−
Analog Power Supply Pin, 5.0V
6 SDATA I
Audio Serial Data Input Pin 2's
complement MSB-first data is input on
this pin.
19 AVSS
−
Analog Ground Pin, 0V
7 LRCK I L/R Clock Input 20 AOUTR- O Rch Negative analog output Pin
8
SMUTE I
Soft Mute Pin in parallel mode When this
pin goes "H", soft mute cycle is initiated.
When returning "L", the output mute
releases.
21 AOUTR+ O Rch Positive analog output Pin
CSN I
Chip Select Pin in serial mode
22 AOUTL- O
Lch Negative analog output Pin
9 DFS0 I
Double speed sampling mode Pin (Internal pull-
down pin) "L": Normal Speed , "H": Double Speed
23 AOUTL+ O Lch Positive analog output Pin
10
DEM0 I De-emphasis Enable Pin in parallel mode 24 VCOM O Common Voltage Output Pin, 2.6V
CCLK I
Control Data Clock Pin in serial mode
25 P/S I
Parallel/Serial Select Pin (Internal pull-up
pin) "L": Serial control mode, "H": Parallel
control mode
11
DEM1 I
De-emphasis Enable Pin in parallel mode
26 CKS0 I Master Clock Select Pin
CDTI I
Control Data Input Pin in serial mode
27 CKS1 I
Master Clock Select Pin
12 DIF0 I Digital Input Format Pin 28 CKS2 I Master Clock Select Pin
13 DIF1 I
Digital Input Format Pin
AK4393VF (MASTER ASSY : IC331)
(BOOTH/REC ASSY : IC201, IC202)
(SEND/RETURN ASSY : IC501)
Pin Arrangement (Top view) Block Diagram
Pin Function