PCM-072/phyCORE-AM64xx System on Module
L-860e.A0
© PHYTEC America L.L.C. 2022
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Figure 23. RGMII PHY Reference Schematics
The circuit consists of:
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An Ethernet PHY to convert the RGMII signals to differential Ethernet signals
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An AND gate to manage Ethernet reset and allow for the user to reset the PHY
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Strapping resistors to manage the PHY settings
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An RJ45 jack for connection to external networks
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A jumper between TX_CLK1, used when the PHY is MII mode, and GTX_CLK1, used when the PHY is in RGMII mode
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A clock fanout buffer to distribute the reference clock signal between the different ethernet PHYs (depending on
the number of Ethernet PHYs you plan to populate, this may or may not be necessary).
7.3 FSI
The phyCORE-AM64xx SOM provides two Fast Serial Interface Transmitter (FSI_TX) cores and six Fast Serial Interface
Receiver (FSI_RX) cores. The FSI cores can be used to communicate with an FSI-enabled device.
