Phytec phyCORE-167CR Hardware Manual Download Page 1

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A product of a PHYTEC Technology Holding company

phyCORE-167CR/

phyCORE-167CS

Hardware Manual

Edition November 2002

Summary of Contents for phyCORE-167CR

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE 167CR phyCORE 167CS Hardware Manual Edition November 2002...

Page 2: ...TEC Me technik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Me technik GmbH further reserv...

Page 3: ...tion of EEPROM FRAM 24 3 10 Second Serial Interface Configuration J13 J14 25 3 11 J15 Address of the Serial EEPROM FRAM 25 3 12 CAN Interfaces J16 J17 J18 J19 26 3 13 J20 Remote Download Source 27 3 1...

Page 4: ...Supply at X1 61 14 3 2 Activating the Bootstrap Loader 63 14 3 3 First Serial Interface at Socket P1A 65 14 3 4 Second Serial Interface at Socket P1B 67 14 3 5 First CAN Interface at Plug P2A 72 14 3...

Page 5: ...g of Jumper Pads 57 Figure 11 Location of the Jumpers View of the Component Side 57 Figure 12 Default Jumper Settings of the phyCORE Development Board HD200 with phyCORE 167CR 167CS 58 Figure 13 Conne...

Page 6: ...gnment of the DB 9 Plug P2B CAN Transceiver on Development Board with Galvanic Separation only with C167CS 81 Figure 23 Pin Assignment Scheme of the Expansion Bus 83 Figure 24 Pin Assignment Scheme of...

Page 7: ...nfiguration 25 Table 13 J15 EEPROM FRAM Address Configuration 25 Table 14 J16 J17 J18 J19 CAN Interface Configuration 27 Table 15 J20 Remote Download Source Configuration 27 Table 16 J21 J22 First Ser...

Page 8: ...2 via Software Emulation 70 Table 35 Improper Jumper Settings for DB 9 Socket P1B 2nd RS 232 via Software Emulation 71 Table 36 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the p...

Page 9: ...2 P3 P4 for the phyCORE 167CR 167CS Development Board Expansion Board 85 Table 49 Pin Assignment Port P5 P6 P7 P8 for the phyCORE 167CR 167CS Development Board Expansion Board 86 Table 50 Pin Assignme...

Page 10: ...phyCORE 167CR 167CS PHYTEC Me technik GmbH 2002 L 527e_8...

Page 11: ...tro Magnetic Conformity of the PHYTEC phyCORE 167CR 167CS PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e...

Page 12: ...ives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE 167CR 167CS is one of a series of PHYTEC Sing...

Page 13: ...lems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package The increased pin package allows...

Page 14: ...rom the controller to high density pitch 0 635 mm connectors aligning two sides of the board allowing it to be plugged like a big chip into a target application Precise specifications for the controll...

Page 15: ...Flash programming no dedicated Flash programming voltage required through use of 5 V Flash devices 256 kByte to 1 MB RAM on board2 up to 21 CAN interfaces with Philips 82C251 CAN transceiver or Silico...

Page 16: ...N E O N C 1 6 7 C R P1 p h y C O R E C o n n e c t o r R S 2 3 2 A d d r F L A S H 256KB 2MB R A M 256KB 1MB P0 D a t a R S 2 3 2 C A N RxD1 TxD1 RxD0 TxD0 CAN0H CAN0L I2 C Bus U A R T R T C RxD0 TxD0...

Page 17: ...to as phyCORE connector This allows the phyCORE 167CR 167CS to be plugged into any target application like a big chip A new numbering scheme for the pins on the phyCORE connector has been introduced w...

Page 18: ...extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCORE connector as well as mating connectors on the phyCORE Development Board or target hardware the...

Page 19: ...d In order to facilitate understanding of the pin assignment scheme the diagram presents a crossview of the phyCORE module showing these phyCORE connectors mounted on the underside of the module s PCB...

Page 20: ...the microcontroller 9A 10A 11A 13A 14A 15A 16A 18A 24A 25A 26A 28A A1 A2 A4 A7 A9 A10 A12 A15 A17 A18 A20 A23 O Address line of the microcontroller 19A 20A 21A 23A 29A 30A 31A 33A D1 D2 D4 D7 D9 D10 D...

Page 21: ...23B 25B 26B 27B A0 A3 A5 A6 A8 A11 A13 A14 A16 A19 A21 A22 O Address line of the microcontroller 18B 20B 21B 22B 28B 30B 31B 32B D0 D3 D5 D6 D8 D11 D13 D14 I O Data line of the microcontroller 33B P3...

Page 22: ...167CS RS 232 level 23C TxD1_RS232 O Output of the second interface series of the phyCORE 167CR 167CS RS 232 level 24C RTS1_RS232 O RTS signal of the UART U7 RS 232 level 25C CTS1_RS232 I CTS signal o...

Page 23: ...2 I Input of the first serial interface RS 232 level 23D TxD0_RS232 O Output of the first serial interface RS 232 level 25D 26D P2 14 P2 15 I O CAPCOM1 CC14 Capture Input Compare Output Fast ext Inter...

Page 24: ...phyCORE 167CR 167CS 14 PHYTEC Me technik GmbH 2002 L 527e_8...

Page 25: ...ery Figure 4 illustrates the numbering of the jumper pads while Figure 5 indicates the location of the jumpers on the board On the phyCORE 167CR 167CS only Jumpers J1 J20 and J23 are located on the to...

Page 26: ...tandard I O at pin header row X1B2 closed IRQ of the UART is connected to P2 8 of the microcontroller J8 open CS2 of the microcon troller is freely available at pin header row X1B6 closed CS2 of the m...

Page 27: ...RT dependens on module configuration J15 2 3 address of the serial memory device at U9 set to 0xA8 hex see Data Sheet of memory device 1 2 address of the serial memory device set to 0xAC hex see Data...

Page 28: ...ce CAN2Rx 2 6 Remote Download Source P3 11 J21 closed 2 P3 11 used as RXD0 and conected to RS 232 transceiver U6 open P3 11 of the controller is freely available as standard I O at pin header row X1D1...

Page 29: ...d at positions 2 3 if the phyCORE 167CR 167CS is populated with external SRAM devices with a total capacity of 2 128 kByte This results in a hard wired connection of VCC to pin 30 of the SRAM If an SR...

Page 30: ...ault setting Table 4 J2 Code Fetch Selection 3 3 J3 Flash Addressing Jumper J3 connects the controller s address line A20 with the address line A19 on the Flash device U1 If using a Flash memory with...

Page 31: ...Jumpers J4 and J5 A D Reference Voltage Source Selection J4 J5 External reference voltage source VAREF at X1D50 VAGND at X1D39 X1D44 and X1D49 open open3 VAREF derived from voltage supply VCC closed...

Page 32: ...CR open Disables oscillator Watchdog of the C167CR 2 3 Connects VPP 12 V at pin 84 for programming of the on chip Flash Note This configuration must not be used in conjunction with an Infineon C167 de...

Page 33: ...External UART 3 7 J9 J10 Configuration of P3 3 P3 4 for I C Bus The phyCORE 167CR 167CS is equipped with a Real Time Clock at U10 and a serial EEPROM FRAM at U9 Both the Real Time Clock and the serial...

Page 34: ...rt P2 9 as INT input for RTC closed Default setting Table 10 J11 RTC Interrupt Configuration 3 9 J12 Write Protection of EEPROM FRAM Various types of EEPROM FRAM can populate space U9 Some of these de...

Page 35: ...1A44 P3 0 and X1A45 P3 1 The following configurations are possible RS 232 Interface Configuration J13 J14 P3 0 and P3 1 connect to RS 232 transceiver for software emulated second serial interface 1 2...

Page 36: ...full 16 MB linear address space of the microcontroller the CAN interface signals can be optionally routed to port 83 In this case Jumpers J16 J19 must be set at positions 1 2 Please refer to the Infi...

Page 37: ...to section 6 Jumper J20 is reserved for future use and remains open as default The following configurations are possible Download Source J20 not available open Port P3 11 RxD0 2 6 Port P3 1 RxD1 1 2 P...

Page 38: ...face signals are available with their TTL level at phyCORE connector pins X1D17 and X1D16 Note These jumpers must remain closed on the phyCORE 167CR 167CS If they are open no serial communication is p...

Page 39: ...al Note Jumper J23 and J24 must be closed in conjunction with the Infineon C167CR or C167CS Microcontroller VCC Pin Connection J23 J24 VCC connected to controller pins closed 1 closed 1 C16 and C17 fu...

Page 40: ...phyCORE 167CR 167CS 30 PHYTEC Me technik GmbH 2002 L 527e_8...

Page 41: ...system startup configuration sets the features of the microcontroller that have a direct influence on program execution and hence the correct execution of the initialization routine as well Of particu...

Page 42: ...ystem reset low byte Bit L7 L6 L5 L4 L3 L2 L1 Bit L0 BUSTYP R22 1 0 SMOD R21 Pin 21B 0 Pin 20B Pin 20A ADP Pin 19A EMU Pin 18B Table 18 Functional Settings on Port P0 for System Startup Configuration...

Page 43: ...6 A23 no I O pins 0 1 no address lines I O pins P4 0 P4 7 0 02 address lines A16 A19 I O pins P4 4 P4 7 CSSEL 1 1 Chip Selects CS0 CS4 no I O pins defines function of port pins P6 0 P6 4 1 0 no Chip S...

Page 44: ...tem startup configuration of the phyCORE 167CR 167CS The initial setting of the system startup configuration can be modified during the initialization routine Certain functions can not be con figured...

Page 45: ...of the Chip Select signals to specific address areas is done with the corresponding ADDRESELx and BUSCONx register Note that ADDRESELx must be configured prior activating of the Chip Select signal wit...

Page 46: ...SR1 RD high until databus high Z max 15 ns Tf SR1 RD high until data high Z rd wr delay max 35 ns Tf SR1 CSx until data valid max 55 ns Tc SR1 RD and WR low min 65 ns Tc CC2 RD and WR low rd wr delay...

Page 47: ...wait 300 ns long ALE 16 bit demultiplexed Example b ADDRESEL1 0006h address range 00 0000h 03 FFFFh 256 kByte RAM bank on U2 3 ADDRESEL2 0806h address range 08 0000h 08 0FFFh 4 kByte address space for...

Page 48: ...kByte I O P6 0 CS0 memory image of Flash Bank 1 P6 3 CS3 P6 4 CS4 P6 0 CS0 FLASH Bank U1 256 kByte RAM Bank U2 U3 P6 1 CS1 256 kByte 256 kByte I O 256 kByte I O P6 0 CS0 memory image of Flash Bank 1 P...

Page 49: ...read write delay no tristate short ALE 16 bit demultiplexed address CSx active This configuration is valid for all memory devices on the phyCORE 167CR 167CS with up to 70 ns access time It activates...

Page 50: ...phyCORE 167CR 167CS 40 PHYTEC Me technik GmbH 2002 L 527e_8...

Page 51: ...connected to the TxD line of the COM port while the TxD0 line is connected to the RxD line of the COM port The Ground potential of the phyCORE 167CR 167CS circuitry needs to be connected to the applic...

Page 52: ...al opto coupler should be implemented to galvanically separate the CAN transceiver and the phyCORE 167CR 167CS This requires the CANTx and CANRx lines to be separated from the on board CAN transceiver...

Page 53: ...he phyCORE 167CR 167CS is equipped with a battery the Real Time Clock runs independently of the board s power supply Programming the Real Time Clock is done via the I2 C bus address 0 x A2 1010001 whi...

Page 54: ...ent Manufacturer EEPROM 4 kByte 24WC32 Catalyst Microchip 8 kByte 24WC64 Catalyst Microchip 32 kByte 24WC256 Microchip FRAM 512 Byte FM24C04 Ramtron 8 kByte FM24C64 Ramtron Table 20 Memory Device Opti...

Page 55: ...ia a BOOT jumper or button This enables a remote controlled software update of the on board Flash device This function can be controlled by various interfaces Solder Jumper J20 configures the remote d...

Page 56: ...ese Flash devices are programmable with 5 V No dedicated pro gramming voltage is required Use of a Flash device as the only code memory results in no or only a limited usability of the Flash memory as...

Page 57: ...f a power failure at VCC the RAM memory and the RTC will be buffered by a connected battery via VBAT The RTC and the SRAM devices are generally supplied via VPD in order to preserve data by means of t...

Page 58: ...cs of this IC are described in the appropriate Data Sheet which is available on the Spectrum CD All pins of the Voltage Supervisor Chip are routed to the phyCORE connector The VPD voltage is available...

Page 59: ...gure 7 The module s profile is ca 6 mm thick with a maximum component height of 2 0 mm on the backside of the PCB and approximately 2 5 mm on the front side The board itself is approximately 1 5 mm th...

Page 60: ...85 C Humidity 95 r F not condensed Operating voltage 5 V 5 VBAT 3 V 20 Power consumption maximum 220 mA typical 110 mA Conditions VCC 5 V VBAT 0 V 256 kByte RAM 5 MHz quartz 20 C maximum 100 A typical...

Page 61: ...buffered To connect external components to the data address bus as well as the control lines RD WR an external buffer i e 74AHCT245 between the modul and the peripheral components should be installed...

Page 62: ...theless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering Overheating the board can cause the solder pads to loosen rendering t...

Page 63: ...ard Computer module The Development Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation...

Page 64: ...on board signals provided by the SBC module mounted on the Development Board are broken out 1 1 to the expansion board by means of its patch field 7 The required connections between SBC module Develop...

Page 65: ...r expansion board connectivity P1 dual DB 9 sockets for serial RS 232 interface connectivity P2 dual DB 9 connectors for CAN or RS 485 interface connectivity X4 voltage supply for external devices and...

Page 66: ...current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user...

Page 67: ...nts are configured for use with the phyCORE 167CR 167CS by means of insertable jumpers If no jumpers are set no signals connect to the DB 9 connectors the control and display units and the CAN transce...

Page 68: ...CS standard C167CR controller use of the RS 232 interface the optional RS 485 interface the CAN interface LED D3 the Boot button on the Development Board Jumper settings for other functional configura...

Page 69: ...r pins for a second supply voltage on the phyCORE 167CR 167CS are not defined Jumper Setting Description JP16 closed VCC2 routed to pins X1C4 and X1C5 on the phyCORE 167CR 167CS Table 21 Improper Jump...

Page 70: ...definition of the VAGND potential is however available in a customer application board 14 3 Functional Components on the phyCORE Development Board HD200 This section describes the functional component...

Page 71: ...power Permissible input voltage 5 VDC regulated The required current load capacity of the power supply depends on the specific configuration of the phyCORE 167CR 167CS mounted on the Development Board...

Page 72: ...hyCORE 167CR 167CS open phyCORE 167CR 167CS not connected to main supply voltage Table 24 JP9 Improper Jumper Settings for the Main Supply Voltage Setting Jumper JP9 to positions 1 2 configures a main...

Page 73: ...RE 167CR 167CS the data line D4 of the microcontroller must be connected to a low level signal at the time the Reset signal changes from its active to the inactive state This is achieved by applying a...

Page 74: ...he power supply Table 26 JP28 Configuration of a Permanent Bootstrap Loader Start 3 It is also possible to start the FlashTools via external signals applied to the DB 9 socket P1A This requires contro...

Page 75: ...d via RTS signal from a host PC open Pin 4 of DB 9 socket P1A not connected JP23 2 32 Boot input of the module can be controlled via DTR signal from a host PC Note JP10 must be set to position 2 3 JP2...

Page 76: ...cted with port P2 15 from phyCORE 167CR 167CS JP23 1 2 Pin 4 of DB 9 socket P1A connected with port P8 0 from phyCORE 167CR 167CS JP24 closed Pin 6 of DB 9 socket P1A connected with port P8 1 from phy...

Page 77: ...1B 1 The phyCORE 167CR 167CS is NOT populated with the optional UART at U7 standard PCM 009 Cx and no serial interface emulation with port pins P3 0 and P3 1 Jumper Setting Description JP1 open Pin 2...

Page 78: ...signal available from the phyCORE 167CR 167CS P1B pin 7 JP4 closed No DSR1_RS232 signal available from the phyCORE 167CR 167CS P1B pin 4 JP5 closed No DTR1_RS232 signal available from the phyCORE 167C...

Page 79: ...ected with CTS1_RS232 signal JP3 open Pin 7 of DB 9 socket P1B not connected closed Pin 4 at P1B is connected with DSR1_RS232 JP4 open Pin 4 of DB 9 socket P1B not connected closed Pin 6 at P1B is con...

Page 80: ...ted JP5 open Pin 6 of DB 9 socket P1B not connected JP6 open Pin 8 of DB 9 socket P1B not connected JP7 open Pin 1 of DB 9 socket P1B not connected JP8 closed Port pin P3 1 of the C167Cx emulates TxD1...

Page 81: ...ed No RI1_TTL signal available from the phyCORE 167CR 167CS P1B pin 9 JP3 closed No CTS1_RS232 signal available from the phyCORE 167CR 167CS P1B pin 7 JP4 closed No DSR1_RS232 signal available from th...

Page 82: ...the DB 9 plug P2A is connected to CAN H0 from on board transceiver on the phyCORE module JP11 open Input at opto coupler U4 on the phyCORE Development Board HD200 open JP12 open Output at opto couple...

Page 83: ...7CR 167CS JP12 1 2 Output at opto coupler U5 on the Development Board connected to CAN1_Rx P8 04 of the C167CR 167CS JP13 2 3 Supply voltage for CAN transceiver and opto coupler derived from local sup...

Page 84: ...Pin 7 of DB 9 plug P2A connected with CAN H0 from on board transceiver on the phyCORE 167CR 167CS JP11 open Input at opto coupler U4 on the Development Board not connected JP12 open Output at opto cou...

Page 85: ...elopment Board connected to CAN1_Tx P8 12 of the C167CR 167CS 2 3 Output at opto coupler U5 on the Development Board connected to CAN1_Rx P4 53 of the C167CR 167CS JP12 1 2 Output at opto coupler U5 o...

Page 86: ...ected with CAN L0 from on board transceiver on the phyCORE 167CR 167CS JP32 2 3 Pin 7 of DB 9 plug P2A connected with CAN H0 from on board transceiver on the phyCORE 167CR 167CS JP11 open Input at opt...

Page 87: ...o CAN L1 from on board transceiver on the phyCORE module JP34 2 3 Pin 7 of the DB 9 plug P2B is connected to CAN H1 from on board transceiver on the phyCORE module JP14 open Input at opto coupler U6 o...

Page 88: ...C67CS 1 2 Output at opto coupler U7 on the Development Board connected to CAN2_Rx P8 24 of the C167CS JP13 open CAN transceiver and opto coupler on the Development Board disconnected from supply volt...

Page 89: ...nnected with CAN_L1 from the on board CAN transceiver on the phyCORE 167CS JP34 2 3 Pin 7 at P2B is connected with CAN_H1 from the on board CAN transceiver on the phyCORE 167CS JP14 open Input at opto...

Page 90: ...cted to CAN2_Tx P8 32 of the C167CS 2 3 Output at opto coupler U7 on the Development Board connected to CAN2_Rx P4 43 of the C167CS JP15 1 2 Output at opto coupler U7 on the Development Board connecte...

Page 91: ...at P2B is connected with TxD1_RS232 from the phyCORE 167CS 1 2 Pin 2 at P2B is connected with P2 5 from the phyCORE 167CS JP33 2 4 Pin 2 at P2B is connected with CAN_L1 from the on board CAN transceiv...

Page 92: ...Patch Field As described in section 14 1 all signals from the phyCORE 167CR 167CS extend in a strict 1 1 assignment to the Expansion Bus connector X2 on the Development Board These signals in turn are...

Page 93: ...wever the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE connector as shown in the following two figures B A D C 80 1 80 1 Figure 23 Pin Assignm...

Page 94: ...P0H 0 D8 28B 28B 37C P0H 1 D9 29A 29A 37E P0H 2 D10 30A 30A 37B P0H 3 D11 30B 30B 37F P0H 4 D12 31A 31A 38A P0H 5 D13 31B 31B 38C P0H 6 D14 32B 32B 38E P0H 7 D15 33A 33A 38B P1L 0 A0 8B 8B 30B P1L 1 A...

Page 95: ...7 CC7IO 16C 16C 5F P2 8 CC8IO EX0IN 2B 2B 28E P2 9 CC9IO EX1IN 3A 3A 28B P2 10 CC10IO EX2IN 3B 3B 28F P2 11 CC11IO EX3IN 19C 19C 6F P2 12 CC12IO EX4IN 20C 20C 7A P2 13 CC13IO EX5IN 37D 37D 12F P2 14 C...

Page 96: ...15 T2EUD 40D 40D 13F P6 0 CS0 49A 49A 44A P6 1 CS1 50A 50A 44E P6 2 CS2 6B 6B 29F P6 3 CS3 5B 5B 29B P6 4 CS4 5A 5A 29E P6 5 HOLD 35B 35B 39B P6 6 HLDA 36A 36A 39D P6 7 BREQ 36B 36B 39F P7 0 POUT0 37B...

Page 97: ...25C 25C 8D DSR1_RS232 26C 26C 9A DTR1_RS232 28C 28C 9F RI1_TTL 29C 29C 10C CD1_TTL 30C 30C 10E SCL 31C 31C 10F SDA 32D 32D 11C Table 50 Pin Assignment Interface Signals for the phyCORE 167CR 167CS Dev...

Page 98: ...D 14D 19D 24D 29D 34D 2A 7A 12A 17A 22A 27A 32A 37A 42A 47A 52A 57A 62A 67A 72A 77A 4B 9B 14B 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B 3C 7C 12C 17C 22C 27C 32C 37C 42C 47C 52C 57C 62C 67C...

Page 99: ...0B 71B 73B 74B 75B 76B 78B 79B 80B 51C 53C 54C 55C 56C 58C 59C 60C 61C 63C 64C 65C 66C 68C 69C 70C 71C 73C 74C 75C 76C 78C 79C 80C 4C 5C 38C 39C 40C 38D 51D 53D 54D 55D 56D 58D 59D 60D 61D 63D 64D 65D...

Page 100: ...er JP28 also refer to section 14 3 2 Jumper Setting Description JP28 7 8 1 3 Boot button S1 can be used to release the NMI interrrupt of the C167CR C167CS controller Table 54 JP28 Releasing the NMI In...

Page 101: ...Number 14 3 12 Pin Header Connector X4 The pin header X4 on the Development Board enables connection of an optional modem power supply Connector X4 supplies 5 V at pin 1 and provides the phyCORE Deve...

Page 102: ...phyCORE 167CR 167CS 92 PHYTEC Me technik GmbH 2002 L 527e_8...

Page 103: ...and is equipped with LEDs for displaying the operating state Since the debugCORE is 100 function compatible with the phyCORE 167CR 167CS it can easily be inserted directly into the application in pla...

Page 104: ...CR 167CS and its reset signal for the purpose of measurement The following table shows the pin layout Pin Signal 1 VCC 2 GND 3 RESET Table 56 Pinout Pin Header Row X3 on the debugCORE 167CR 167CS Two...

Page 105: ...67CR 167CS to an Emulator The debugADAPTER 167 is inserted into the SMD socket at X2 on the debugCORE The debugADAPTER 167 features a Quad Connector which enables direct connection of an Emulator with...

Page 106: ...l Pin 1 NC NC 2 3 P6 0 P6 1 4 5 P6 2 P6 3 6 7 P6 4 HLD P 8 9 P6 6 P6 7 10 11 P8 0 P8 1 12 13 P8 2 P8 3 14 15 P8 4 P8 5 16 17 P8 6 P8 7 18 19 VCC GND 20 21 P7 0 P7 1 22 23 P7 2 P7 3 24 25 P7 4 P7 5 26...

Page 107: ...8 A19 98 99 A20 A21 100 101 A22 A23 102 103 VCC GND 104 105 RD P WRL 106 107 RDY P ALE 108 109 EA D0 110 111 D1 D2 112 113 D3 D4 114 115 D5 D6 116 117 D7 D8 118 119 NC NC 120 Pin Signal Signal Pin 121...

Page 108: ...on header the debugCORE s physical dimensions are greater than those of its phyCORE base module This must be taken into consideration especially upon insertion into the target application Dimensions d...

Page 109: ...Connector X4 91 D Development Board Connectors and Jumpers 55 Dimensions 50 DS2401 90 E EEPROM 23 EMC 1 Expansion Bus 82 External UART 22 F Features 5 First CAN Interface 72 First Serial Interface 65...

Page 110: ...upply 61 Programming Voltage 22 R Real Time Clock 43 Reference Voltage 21 Remote Supervisory Chip 45 Reset Button 57 RS 232 Interface 41 RS 232 Level 41 RS 232 Transceiver 41 RTC 23 47 RTC Interrupt O...

Page 111: ...k GmbH 2002 L 527e_8 101 U U1 46 U10 23 43 U11 42 U12 42 U2 19 U3 19 U4 51 U5 41 U6 41 U7 41 U8 45 U9 23 44 UART 41 UART external 41 UART on chip 41 V VAGND 21 VAREF 21 VBAT 47 Voltage Supervisor Chip...

Page 112: ...phyCORE 167CR 167CS 102 PHYTEC Me technik GmbH 2002 L 527e_8...

Page 113: ...167CR 167CS Document number L 527e_8 November 2002 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC T...

Page 114: ...Published by PHYTEC Me technik GmbH 2002 Ordering No L 527e_8 Printed in Germany...

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