Panasonic UF-5500, Service Manual

Page: 193 / 365

193
UF-5500 / 4500
IC750 (C1CB00002566 : 3.3V Single Power Supply) Pin Description
Pin No Signal Name Input/Output(*) Description
1 GND Gnd Ground
2 VDDPLL_1.8 P 1.8V analog VDD
3 VDDA_3.3 P 3.3V analog VDD
4 RX- I/O Physical receive or transmit signal (- differential)
5 RX+ I/O Physical receive or transmit signal (+ differential)
6 TX- I/O Physical transmit or receive signal (- differential)
7 TX+ I/O Physical transmit or receive signal (+ differential)
8 XO O Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or
if RMII mode is selected.
9 XI / REFCLK I Crystal / Oscillator / External Clock Input
MII Mode: 25MHz +/-50ppm (crystal, oscillator, or external clock) RMII
Mode: 50MHz +/-50ppm (oscillator, or external clock only)
10 REXT I/O Set physical transmit output current
Connect a 6.49K
Ω
resistor in parallel with a 100pF capacitor to ground
on this pin. See KSZ8041NL reference schematics.
11 MDIO I/O Management Interface (MII) Data I/O
This pin requires an external 4.7K
Ω
pull-up resistor.
12 MDC I Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13 RXD3 / PHYAD0 Ipu/O MII Mode: Receive Data Output[3](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0]
during power-up / reset. See “Strapping Options” section for details.
14 RXD2 / PHYAD1 Ipd/O MII Mode: Receive Data Output[2](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1]
during power-up / reset. See “Strapping Options“ section for details.
15 RXD1 /
RXD[1] /
PHYAD2 Ipd/O MII Mode: Receive Data Output[1](2) /
RMII Mode: Receive Data Output[1](3) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2]
during power-up / reset. See “Strapping Options“ section for details.
16 RXD0 /
RXD[0] /
DUPLEX Ipu/O MII Mode: Receive Data Output[0](2) /
RMII Mode: Receive Data Output[0](3) /
Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options“ section for details.
17 VDDIO_3.3 P 3.3V digital VDD
18 RXDV /
CRSDV /
CONFIG2 Ipd/O MII Mode: Receive Data Valid Output /
RMII Mode: Carrier Sense/Receive Data Valid Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG2 dur-
ing power-up / reset. See “Strapping Options“ section for details.
19 RXC O MII Mode: Receive Clock Output
20 RXER /
RX_ER /
ISO Ipd/O MII Mode: Receive Error Output /
RMII Mode: Receive Error Output /
Config Mode: The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options“ section for details.
21 INTRP Opu Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming
the interrupt conditions and reading the interrupt status. Register 1Fh bit
9 sets the interrupt output to active low (default) or active high.
22 TXC O MII Mode: Transmit Clock Output
23 TXEN / TX_EN I MII Mode: Transmit Enable Input /
RMII Mode: Transmit Enable Input
24 TXD0 / TXD[0] I MII Mode: Transmit Data Input[0](4) /
RMII Mode: Transmit Data Input[0](5)
25 TXD1 / TXD[1] I MII Mode: Transmit Data Input[1](4) /
RMII Mode: Transmit Data Input[1](5)
26 TXD2 I MII Mode: Transmit Data Input[2](4) /
27 TXD3 I MII Mode: Transmit Data Input[3](4) /
28 COL / CONFIG0 Ipd/O MII Mode: Collision Detect Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG0 dur-
ing power-up / reset. See “Strapping Options“ section for details.
29 CRS / CONFIG1 Ipd/O MII Mode: Carrier Sense Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG1 dur-
ing power-up / reset. See “Strapping Options“ section for details.