Panasonic PV-D4733S-K, Service Manual

Page: 62 / 274

NOTE:
FOR SCHEMATIC DIAGRAM AND CIRCUIT BOARD LAYOUT NOTES,
REFER TO BEGINNING OF SCHEMATIC SECTION.
NOTE: For placing a purchase order of the parts,
be sure to use the part number listed in the parts list.
Do not use the part number on this diagram.
NOTE:
PARTS MARKED "PT" ARE NOT USED.
COMPARISON CHART
OF MODELS & MARKS
PV-D4733S-K
- - - - - - - -
PV-D4753S-K
- - - - - - - -
PV-D4763S-K
Not Used
A
B
C
D
E
PT
MODEL
MARK
PV-D4763S-K
I/O CHART OF IC2001
IC2002 IC- DETAIL BLOCK DIAGRAM
Pin No. I/O
I 1
Signal Name Description
VCC +3.3V
I/O 2 DQ0 SDRAM data 0
+3.3V
SDRAM data 1
SDRAM data 2
Ground
SDRAM data 3
SDRAM data 5
SDRAM data 6
Ground
SDRAM data 7
+3.3V
Lower Data output/input mask
Write enable : low
SDRAM chip select : low
SDRAM address 13
SDRAM address 12
SDRAM address 10
SDRAM address 0
I 3 VCCQ
I/O 4 DQ1
I/O 5 DQ2
- 6 VSSQ
I/O 7 DQ3
I/O 8 DQ4 SDRAM data 4
Column address strobe : low
SDRAM address 3
SDRAM address 9
I 9 VCCQ +3.3V
I/O 10 DQ5
I/O 11 DQ6
- 12 VSSQ
I/O 13 DQ7
I 14 VCC
I 15 LDQM
I 16 WE-
I 17 CSA-
I 18 RAS- Row address strobe : low
I 19 CS-
I 20 A13
I 21 A12
I 22 A10
I 23 A0
I 24 A1 SDRAM address 1
I 25 A2 SDRAM address 2
Ground
SDRAM address 4
SDRAM address 5
SDRAM address 6
(Not used)
SDRAM clock enable
SDRAM clock
SDRAM data 8
SDRAM data 10
Ground
SDRAM data 11
SDRAM data 12
SDRAM data 13
I 26 A3
I 27 VCC +3.3V
- 28 VSS
I 29 A4
I 30 A5
A6 I 31
I 32 A7 SDRAM address 7
I 33 A8 SDRAM address 8
I 34 A9
I 35 A11 SDRAM address 11
- 36 NC
I 37 CKE
I 38 CLK
I 39 UDQM Upper Data input/output mask
(Not used) - 40 NC
- 41 VSS Ground
I/O 42 DQ8
I 43 VCCQ +3.3V
Ground
I/O 44 DQ9 SDRAM data 9
I/O 45 DQ10
- 46 VSSQ
I/O 47 DQ11
I/O 48 DQ12
I 49 VCCQ +3.3V
I/O 50 DQ13
I/O 51 DQ14 SDRAM data 14
- 52 VSSQ
I/O 53 DQ15 SDRAM data 15
Ground - 54 VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
VDD
VDD
GND
GND
VDD
SD CS(L)
SD READY(L)
VDD
V POWER SAVE
VDD
GND
SERIAL DATA
SERIAL CLOCK
SERIAL DATA
SD RESET(L)
VDD VDD VDD VDD GND GND VDD GND GND
VIDEO MUTE
R-Y/B-Y
SD IRQ
CLOCK
SD RESET(L)
ENCODER RESET(L)
DSP EX TERNAL FLAG
I
2
C SERIAL DATA
I 2 C SERIAL CLOCK
VDD
H-SYNC V-SYNC
VDD GND GND VDD
VDD
27MHz CLOCK
27MHz CLOCK
GND
SDRAM ROW ADDRESS STROBE : LOW
SDRAM COLUMN ADDRESS STROBE : LOW
GND
VDD
GND
VDD
VDD
VDD
GND
GND
SDRAM UPPER DATA INPUT / OUTPUT MASK
SDRAM LOWER DATA INPUT / OUTPUT MASK
SDRAM WRITE ENABLE : LOW
SDRAM CHIP SELECT : LOW
SDRAM CLOCK ENABLE
CLOCK
VDD GND GND VDD VDD VDD GND GND VDD VDD GND
SDRAM CLOCK EM CS 0 EM CS 4 SD CHIP SELECT (L) SD WRITE ENABLE SD OUTPUT ENABLE
ADDRESS BUS
VIDEO INTER FACE
OSD
BURST
CODEC
MEMORY INTER FACE
VDD
ADDRESS BUS
DATA BUS
VDD GND
DATA BUS
C Y
I/O CHART OF IC2001 IC2002 IC- DETAIL BLOCK DIAGRAM