Panasonic Panafax UF-585, Service Manual

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In the actual circuit, the fixed output voltages are obtained by changing the winding ratio of transformer T101. In this converter
circuit, the output voltages are stabilized by controlling the duty cycle of the ON and OFF timing of the transistor. In this power
supply, the bias winding is built into the transformer. The power supply has four outputs, +24 VDC, -12 VDC, +5 VP and +5
VDC. The +24 VDC output is protected by the Error Detection Circuit, and the +5 VP and -12 VDC outputs are protected by the
circuitry inside of the voltage regulator IC, +5 VDC is protected by ZD251.
Control Circuit and Error Detection Circuit
The control circuit amplifies the output of the duty cycle according to the error voltage detected by the Error Detection Circuit,
and drives the main transistor Q101. The method used to change the duty cycle is to change the ON time period. When the
output voltage of the +24 VDC circuit rises, the current of photocoupler PC101 increases, the output pulse width of the control
circuit decreases and the ON time period of Q101 decreases. This control circuit decides the minimum OFF time period by itself.
When the oscillation frequency becomes higher and the OFF time period becomes minimum, the OFF time period remains
unchanged and only the ON time period decreases. This way, there is a upper limit of the oscillation frequency and the duty
cycle is expanded.
Over Current Limiter (O.C.L)
The +24 VDC output is limited by Ton MAX Limiter (ON time period of transistor Q101) which is part of the control circuit. The +5
VP, -12 VDC and +5 VDC outputs have over current limiters provided inside the voltage regulator and IC251.
The value of output voltage is
Eo=d/(1-d)*Ei
d=Ton/Ts
Equivalent circuit model for the RCC.
Ton : ON time of Q102
In the equivalent circuit ; When SW is ON, current
flows
SW L
When SW is OFF, current flows
L D RL
The value of inductance increase current between
ON period. (d*Ts)
IL=Ei/L*d*Ts . . . . . . . . . . . . . . . . . .(1)
The value of inductance decrease current between
OFF period. ((1-d)*Ts) . . . . . . . . . . . . . . . .(2)
From equation (1) and (2),
E0=d/(1-d)*Ei
Ts : Period of oscillation
VL
VL
L C
T101
D(D203)
Eo
Eo
Ts dTs
RL
Ei
SW
(Q101)
T
IL
Ei
(1-d)Ts dTs