Panasonic KX-FP701ME, Service Manual

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KX-FP701ME
6.3.4. Flash Memory (IC6)
This 512KB ROM (FLASH MEMORY) carries a common area of 32KB and bank areas which each have 8KB (BK4~BK63). The
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
6.3.5. Dynamic RAM (IC4)
The DRAM serves as CPU and receives memory.
The address is F200H~F3FFH (DRAM access window 1) and F600H~F7FFH (DRAM access window 2).
114 XRESETI I 3.3V RESET INPUT
115 WDERR O 3.3V WATCHED ERROR OUTPUT SIGNAL
116 THDAT O 3.3V RECORDED IMAGE OUTPUT (XTHDAT)
117 THCLK O 3.3V CLOCK OUTPUT FOR DATA TRANSFER (XTHCLK)
118 THLAT O 3.3V PULSE OUTPUT FOR DATA LATCH (XTHLAT)
119 STBNP I 0V INPUT PORT (NOT USED)
120 RM0/IOP O 3.3V RX MOTOR A PHASE
121 RM1/IOP I/O 3.3V RX MOTOR B PHASE
122 RM2/IOP I/O 3.3V RX MOTOR /A PHASE
123 RM3/IOP I/O 3.3V RX MOTOR /B PHASE
124 RXE/IOP O 3.3V RX MOTOR ENABLE
125 TMO O 3.3V TX MOTOR A PHASE
126 VDD (2.5V) ----- POWER SOURCE (+2.5V)
127 VSS GND POWER SOURCE (GND)
128 TM1/IOP O 3.3V TX MOTOR B PHASE
129 TM2/IOP O 3.3V TX MOTOR /A PHASE
130 TM3/IOP O 3.3V TX MOTOR /B PHASE
131 TXE/IOP O 3.3V TX MOTOR ENABLE
132 KSTART O 3.3V OPERATION PANEL CONTROL
133 KLATCH O 3.3V OPERATION PANEL CONTROL
134 KSCLK O 3.3V OPERATION PANEL CONTROL
135 KTXD O 3.3V OPERATION PANEL CONTROL
136 KRXD I 3.3V OPERATION PANEL CONTROL
137 FMEMCLK/IOP O 3.3V OUTPUT PORT (OP RESET)
138 FMEMDI/IOP O 3.3V OUTPUT PORT (SP MUTE)
139 ADSEL1 O 3.3V CHANNEL SELECT SIGNAL FOR AIN2
140 VDDA (2.5V) 2.5V POWER SOURCE (2.5V)
141 VREFB A 3.3V A/D CONVERTER'S ZERO STANDARD VOLTAGE
OUTPUT
142 VCL A 3.3V ANALOG PART STANDARD VOLTAGE SIGNAL
143 VREFT A 3.3V A/D CONVERTER'S FULL SCALE VOLTAGE OUTPUT
144 VSSA GND POWER SOURCE (ANALOG GND)
NO. SIGNAL I/O POWER SUPPLIED
VOLTAGE
DESCRIPTION