Oki Dr.63514, User Manual, Page: 35 / 101

Chapter 2. Functions
2-14
The break timing is not immediately after the instruction satisfying the break condition, but an additional
instruction later.
Specifying a code memory address produces a break only if the instruction at that address is a ROM
table reference instruction.
(6) Internal ROM table address match break
Execution breaks when a ROM table reference instruction (MOVHB or MOVLB) reads from the specified
code memory address.
Specifying a ROM table address of 800H
produces a break one instruction after
the MOVHB [HL+],800H instruction at
address 401H, that is, after the NOP
instruction at address 403H.
ROM table
400H
401H
403H
800H
801H
802H
404H
68H
53H
22H
33H
57H
28H
NOP
MOVHB [HL+], 800H
NOP
NOP
The break timing is not immediately after the instruction satisfying the break condition, but an additional
instruction later.
There is a bit mask parameter for extending address checking to multiple ROM table addresses.
This type of break provides no count parameter.
n
Note 5
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Address settings at the following addresses never produce address breaks or address pass
count breaks—unless there is something seriously wrong with the user application program.
(a) ROM table locations
100H
101H
102H
The address 323H never
produces an address break.
323H
Break address
NOP
MOVLB [HL], 323H
Table data