Oki Dr.63514, User Manual, Page: 34 / 101

Chapter 2. Functions
2-13
300H
301H
302H
303H
Specifying an address of 300H and a
c o u n t o f 2 p r o d u c e s a b r e a k o n e
i n s t r u c t i o n a f t e r t h e M O V [ H L ] , A
instructions at addresses 303H and 305H,
that is, after the NOP instruction at
address 306H.
304H
305H
306H
RAM read
instruction
RAM write
instruction
MOV CBR,#3H
MOV H,#0H
MOV L,#0H
MOV [HL],A
NOP
MOV [HL],A
NOP
The break timing is not immediately after the instruction satisfying the break condition, but an additional
instruction later.
There is a bit mask parameter for extending address checking to multiple data memory addresses.
n
Note 4
n
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RAM address match breaks are available over the entire data memory address space—even
SFR addresses.
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(5) Internal ROM table data match break
Execution breaks when a ROM table reference instruction (MOVHB or MOVLB) reads either any data or
the specified data from the specified code memory address.
There is a bit mask parameter for extending data checking to multiple (or even all) comparison values.
This type of break provides no count parameter.
Specifying a ROM table address of 300H
and a comparison value of 33H produces
a break one instruction after the MOVLB
[HL],300H instruction at address 101H,
that is, after the NOP instruction at
address 102H.
100H
101H
102H
300H
301H
302H
LOW HIGH
ROM table
38H
50H
33H
24H
60H
28H
NOP
MOVLB [HL], 300H
NOP