Novametrix Medical Systems OXYPLETH 520A, Service Manual

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Section 9
Electronic Theory of Operation
32
Model 520A Service Manual 5693-90-01
PRELIMINARY
If the WDOG pulse does not appear at regular intervals, as the result of a software
or hardware problem, the RC charges up and IC21 pin 8 goes low producing a
Watchdog Time-out (WDTO*) input at IC18 pin 11. WDTO* combines with other
signals within the PEEL and causes the open drain Master Reset (MR) output at
IC18 pin 13 to be brought low.
A low MR causes C45 to discharge, forcing IC21 pin6 high. This sends a reset pulse
to the system. It also sets the Reset Input (RESIN) signal at IC18 pin 9 high which
causes RESET* at IC18 pin 19 to activate low. The active RESET line causes the
microprocessor (IC16 pin 7) and the display module to be reset. The monitor then
performs its powerup self-test routines, and if the “glitch” has been cleared, the
monitor resumes normal operation. If the problem still exists, a self-test or other
error should be displayed.
Serial I/O Controller
9.3.22
Digital data from the three Analog-To-Digital Convertors is read by the CPU
through its clocked serial data input (RXS) at IC16 pin 52. The PEEL IC18 acts as
the Clocked Serial I/O (CSI/O) Controller.
Except during powerup or Watchdog Timer reset,IC39 pin 3 provides an interrupt
to the CSI/O controller in the form of a 5 millisecond period square-wave input to
IC18 pin 7 (INT5MS).
On the rising edge of INT5MS, a CPU interrupt request is generated when IC18 pin
18 (CPUINIT*) goes low. The CPU responds by sending the clock input to CSI/O
controller (CKS) at IC18 pin 6 low. (This CKS line is inactive high unless a serial
receive operation is in progress.) The CPU also sets up the ADC decode lines AA1
and AA0 at IC18 pins 5 and 4, and as a result, one of the ADC chip select lines
(CSADC1*, CSADC2*, CSADC3*) is brought low, and the CPUINIT* line is
disabled.
On the rising CKS signal a CLKS output pulse at IC18 pin 14 is sent as a serial clock
input to the ADC selected by the decode lines. Decode results are shown below.
Successive CKS/CLKS pulses cause the ADC data to be shifted out of the ADC
(most significant bit first) along the serial data line (SDATA) to the CPU serial
input (RXS) at IC16 pin 52.
AA1 AA0 Decode
0 0 Red LED 20-bit ADC
0 1 Infrared LED 20-bit ADC
1 1 Sensor Status 8-bit ADC
1 0 Internal CSI/O signal (TEND)
Table 2. CSI/O Decode Lines