Novametrix Medical Systems OXYPLETH 520A, Service Manual

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2471 & 2775 Main Board
5-Jun-01 Model 520A Service Manual
31
PRELIMINARY
The backlight for the display is controlled by the DSPBR (Display Bright) line.
When DSPBR is high the gate of Q16 is biased off, current flows from Vcc through
R51 to IC45. This sets the backlight for low illumination. The illumination of the
backlight is made greater when DSPBR is made low, this biases Q16 on which
essentially shorts out R51 allowing more current to flow into IC45 creating a full
backlight.
I/O Device Controller
9.3.20
The A/D Converter Chip Selects, serial A/D Chip Selects, Sensor Status Decoding
and NEXT* line are all controlled by IC28 when selected by the OPORT line (IC21
pin 10). The OPORT line will go high when the L1* and WR* line both go low at
IC23 pins 13 and 12, this will send output pin IC23 pin 11 low which drives inverter
IC21 pin 10 high enabling IC28.
A 3 to 8 decoder is used to control the DACCS*, RTC*, DISPC*, AUD*, KEYS*,
L1*, L2*, 2KEYS* lines. when the IOE* line goes low and the LIR* line goes high
being inverted by IC21 pin 2 and presented to IC22 pin 5 as a low enable line IC22
is enabled, Q0-Q7 will be driven low depending upon the A4, A5 and A6 lines on
pins 1, 2, 3 respectively on IC22.
With the LPORT line high IC13 is enabled, this latches the data on lines D0-D7
(1D-8D pins 2-9) on its output pins 19-12 (1Q-8Q respectively), the outputs
correspond to the following eight lines:
CAL-used by the A/D Convertors on power up to compensate for front end voltage
offsets.
TML-Two Minute LED drives the
LED on the front display.
AOL-Audio Out LED drives the LED on the front panel.
ARL-Alert LED drives the LED on the front panel.
KJL*-drives Q17 when high which in turn drives the Alert Bar LEDs via J105.
BTL-Battery Low
LED on the front panel.
DSPBR-(not used on the 520A)
OFFDIS-sent to the Power On/Off section of the circuitry to prevent the monitor
from being turned off while writing to RAM.
Watchdog Timer
9.3.21
The Watchdog Timer provides a system reset function in the event a hardware or
software “glitch” occurs. The PEEL IC18 forms the heart of the Watchdog circuit.
(See sheet 2 on 2471 schematic, sheet 1 on 2775 schematic.)
At powerup and at specific intervals thereafter, the microprocessor outputs a logic
high to IC18 pin 8, WDOG (Watchdog). The WDOG signal combines with other
signals within the PEEL and as a result the Watchdog Clear (WDCLR) open drain
output at IC18 pin 12 is continually brought low. This discharges the capacitor C46
before it can charge up (via RP2 pins 1 and 2) past the input threshold of IC21 pin 9.