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4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Figure 4-3-1 FPGA Processing Block Diagram
Note: When Test Pattern is selected, Black/White reference, Digital Gain & Offset are
omitted.
4.4 Startup
After turning on, the camera run a startup procedure before it starts getting images
and outputting data. It takes about ten seconds.
The start-up is executed by the following sequence, and as for the camera, the
preparation for the image acquisition and the output is complete when normally
ending.
(1)The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After this sequence, the camera is ready to get images and output data.
