35 NED
XCM
4085TLCT6
UME-0062-01
4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Figure 4-3-1 FPGA Processing Block Diagram
4.4 Startup
After turning on, the camera runs a startup procedure before it starts getting
images and outputting data. It takes about 15 seconds.
The startup procedure is as follows:
.
(1) The camera hardware initializes. The indicator (LED green) blinks.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
The indicator (LED green) changes from blinking into lighting.
After those sequences, the camera is ready to get images and output data.
4.5 Saving and Loading Camera Settings
The camera settings data is saved in the internal memory (flash memory) and is
loaded from the memory when turning on the power supply or loading (sending the
“rfd” command).
Commands for rewriting the memory are as follows.
Reset to factory settings (rst)
Store present setup data in memory (sav)
Store pixel correction data in memory (wht)
Video Data
From Sensor
-
x
Bright image reference
multiplication
Dark image reference
subtract
x
Digital Gain
Value Set
+/-
Digital Offset
Value Set
8 or 10bit select &
1 or 2tap select
Flat Field Correction
Digital Gain & Offset
Output Format
Video(8 or 10bit)
To Channel Link Driver
Delay line number
Set
Line Delay
