User’s Manual U14826EJ5V0UD
15
LIST OF FIGURES (1/4)
Figure No.
Title
Page
3-1 Pin
I/O
Circuits ................................................................................................................................................38
4-1
Memory Map (
µ
PD789860, 789861)...............................................................................................................39
4-2
Memory Map (
µ
PD78E9860A, 78E9861A) .....................................................................................................40
4-3
Data Memory Addressing (
µ
PD789860, 789861) ...........................................................................................42
4-4
Data Memory Addressing (
µ
PD78E9860A, 78E9861A) ..................................................................................43
4-5 Program
Counter Configuration ......................................................................................................................44
4-6
Program Status Word Configuration ...............................................................................................................44
4-7 Stack
Pointer
Configuration ............................................................................................................................45
4-8
Data to Be Saved to Stack Memory ................................................................................................................45
4-9
Data to Be Restored from Stack Memory .......................................................................................................45
4-10 General-Purpose
Register Configuration ........................................................................................................46
5-1 EEPROM
Block Diagram ................................................................................................................................58
5-2
Format of EEPROM Write Control Register 10 ...............................................................................................59
6-1 Block
Diagram
of P00 to P07 ..........................................................................................................................64
6-2 Block
Diagram of P20 .....................................................................................................................................65
6-3 Block
Diagram of P21 .....................................................................................................................................66
6-4 Block
Diagram
of P40 to P43 ..........................................................................................................................66
6-5
Format of Port Mode Register.........................................................................................................................67
7-1 Block
Diagram
of Clock Generator..................................................................................................................69
7-2
Format of Processor Clock Control Register...................................................................................................70
7-3
External Circuit of System Clock Oscillator .....................................................................................................71
7-4
Examples of Incorrect Resonator Connection.................................................................................................72
7-5
Switching Between System Clock and CPU Clock .........................................................................................75
8-1 Block
Diagram
of Clock Generator..................................................................................................................76
8-2
Format of Processor Clock Control Register...................................................................................................77
8-3
External Circuit of System Clock Oscillator .....................................................................................................78
8-4
Examples of Incorrect Resonator Connection.................................................................................................79
8-5
Switching Between System Clock and CPU Clock .........................................................................................82
9-1
Timer 30 Block Diagram .................................................................................................................................85
9-2
Timer 40 Block Diagram .................................................................................................................................86
9-3
Block Diagram of Output Controller (Timer 40) ...............................................................................................87
