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CHAPTER 13 PLL FREQUENCY SYNTHESIZER
User’s Manual U15104EJ2V0UD
(1) PLL data register L (PLLRL), PLL data register H (PLLRH), and PLL data register 0 (PLLR0)
These registers set the division value of the PLL frequency synthesizer. The division value of the PLL
frequency synthesizer is made up of 17 bits. The higher 16 bits of this value are set by PLL data register L
(PLLRL) and PLL data register H (PLLRH). The higher 16 bits can also be set by the PLL data register (PLLR).
The least significant bit is set by bit 7 (PLLSCN) of PLL data register 0 (PLLR0).
Reset input makes the contents of these registers undefined. These registers hold the current values in the
STOP and HALT modes.
(2) Input select block
The input select block consists of the VCOL and VCOH pins, and input amplifiers of the respective pins.
(3) Programmable divider
The programmable divider consists of two modulus prescalers, a programmable counter (12 bits), a swallow
counter (5 bits), and a division mode select switch.
(4) Reference frequency generator
The reference frequency generator consists of a divider that generates the reference frequency f
r
of the PLL
frequency synthesizer, and a multiplexer.
(5) Phase comparator
The phase comparator (
φ
-DET) compares the phase of the divided frequency output f
N
of the programmable
divider with that of the reference frequency output f
r
of the reference frequency generator, and outputs an up
request signal (UP) and down request signal (DW).
(6) Unlock F/F
The unlock F/F detects the unlock status of the PLL frequency synthesizer from the up request signal (UP)
and down request signal (DW) of the phase comparator (
φ
-DET).
(7) Charge pump
The charge pump outputs the result of the output of the phase comparator from the error out pins (EO0 and
EO1 pins).
